Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13977452	9789	0	0
alert_regwen_rd_A	13977452	6555	0	0
cpu_regwen_rd_A	13977452	6437	0	0
sw_rst_ctrl_n_0_rd_A	13977452	11561	0	0
sw_rst_ctrl_n_1_rd_A	13977452	11740	0	0
sw_rst_ctrl_n_2_rd_A	13977452	11473	0	0
sw_rst_ctrl_n_3_rd_A	13977452	11741	0	0
sw_rst_ctrl_n_4_rd_A	13977452	11599	0	0
sw_rst_ctrl_n_5_rd_A	13977452	11574	0	0
sw_rst_ctrl_n_6_rd_A	13977452	11444	0	0
sw_rst_ctrl_n_7_rd_A	13977452	11511	0	0
sw_rst_regwen_0_rd_A	13977452	7020	0	0
sw_rst_regwen_1_rd_A	13977452	7095	0	0
sw_rst_regwen_2_rd_A	13977452	6812	0	0
sw_rst_regwen_3_rd_A	13977452	7009	0	0
sw_rst_regwen_4_rd_A	13977452	6860	0	0
sw_rst_regwen_5_rd_A	13977452	6594	0	0
sw_rst_regwen_6_rd_A	13977452	6922	0	0
sw_rst_regwen_7_rd_A	13977452	6875	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	9789	0	0
T56	11287	1	0	0
T57	19520	3	0	0
T59	2107	30	0	0
T60	2027	250	0	0
T61	4019	170	0	0
T67	20279	3	0	0
T74	19899	4	0	0
T75	4934	409	0	0
T76	4148	15	0	0
T77	11858	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6555	0	0
T11	320728	521	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	59	0	0
T87	0	270	0	0
T88	0	398	0	0
T89	0	230	0	0
T90	0	31	0	0
T109	0	382	0	0
T110	0	89	0	0
T111	0	124	0	0
T112	0	31	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6437	0	0
T11	320728	481	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	60	0	0
T87	0	221	0	0
T88	0	447	0	0
T89	0	207	0	0
T90	0	34	0	0
T109	0	372	0	0
T110	0	82	0	0
T111	0	142	0	0
T112	0	55	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11561	0	0
T11	320728	757	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	74	0	0
T40	0	77	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	83	0	0
T87	0	347	0	0
T88	0	495	0	0
T89	0	350	0	0
T113	0	132	0	0
T114	0	59	0	0
T115	0	154	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11740	0	0
T11	320728	727	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	41	0	0
T40	0	86	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	66	0	0
T87	0	370	0	0
T88	0	529	0	0
T89	0	358	0	0
T113	0	148	0	0
T114	0	58	0	0
T115	0	179	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11473	0	0
T11	320728	704	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	63	0	0
T40	0	59	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	73	0	0
T87	0	357	0	0
T88	0	543	0	0
T89	0	396	0	0
T113	0	173	0	0
T114	0	46	0	0
T115	0	139	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11741	0	0
T11	320728	672	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	44	0	0
T40	0	63	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	61	0	0
T87	0	329	0	0
T88	0	588	0	0
T89	0	443	0	0
T113	0	120	0	0
T114	0	63	0	0
T115	0	161	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11599	0	0
T11	320728	732	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	64	0	0
T40	0	63	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	77	0	0
T87	0	375	0	0
T88	0	537	0	0
T89	0	409	0	0
T113	0	120	0	0
T114	0	56	0	0
T115	0	171	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11574	0	0
T11	320728	716	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	48	0	0
T40	0	40	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	72	0	0
T87	0	338	0	0
T88	0	515	0	0
T89	0	343	0	0
T113	0	142	0	0
T114	0	42	0	0
T115	0	160	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11444	0	0
T11	320728	732	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	49	0	0
T40	0	70	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	70	0	0
T87	0	319	0	0
T88	0	509	0	0
T89	0	324	0	0
T113	0	157	0	0
T114	0	69	0	0
T115	0	171	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	11511	0	0
T11	320728	693	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T38	0	50	0	0
T40	0	59	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	75	0	0
T87	0	341	0	0
T88	0	553	0	0
T89	0	400	0	0
T113	0	143	0	0
T114	0	46	0	0
T115	0	149	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	7020	0	0
T11	320728	497	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	60	0	0
T87	0	236	0	0
T88	0	400	0	0
T89	0	224	0	0
T90	0	21	0	0
T113	0	39	0	0
T115	0	42	0	0
T116	0	13	0	0
T117	0	55	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	7095	0	0
T11	320728	505	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	60	0	0
T87	0	247	0	0
T88	0	395	0	0
T89	0	279	0	0
T90	0	39	0	0
T113	0	19	0	0
T115	0	24	0	0
T116	0	9	0	0
T117	0	30	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6812	0	0
T11	320728	475	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	86	0	0
T87	0	245	0	0
T88	0	467	0	0
T89	0	182	0	0
T90	0	33	0	0
T113	0	26	0	0
T115	0	37	0	0
T116	0	12	0	0
T117	0	25	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	7009	0	0
T11	320728	555	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	85	0	0
T87	0	223	0	0
T88	0	369	0	0
T89	0	226	0	0
T90	0	44	0	0
T113	0	34	0	0
T115	0	28	0	0
T116	0	9	0	0
T117	0	12	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6860	0	0
T11	320728	482	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	78	0	0
T87	0	256	0	0
T88	0	395	0	0
T89	0	239	0	0
T90	0	26	0	0
T113	0	29	0	0
T115	0	37	0	0
T116	0	5	0	0
T117	0	37	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6594	0	0
T11	320728	544	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	60	0	0
T87	0	214	0	0
T88	0	359	0	0
T89	0	221	0	0
T90	0	2	0	0
T113	0	39	0	0
T115	0	30	0	0
T116	0	9	0	0
T117	0	36	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6922	0	0
T11	320728	472	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	87	0	0
T87	0	208	0	0
T88	0	407	0	0
T89	0	234	0	0
T90	0	38	0	0
T113	0	27	0	0
T115	0	24	0	0
T116	0	7	0	0
T117	0	40	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13977452	6875	0	0
T11	320728	499	0	0
T12	72120	0	0	0
T13	4654	0	0	0
T14	4483	0	0	0
T22	220460	0	0	0
T23	154929	0	0	0
T55	7259	0	0	0
T62	5277	0	0	0
T70	5650	0	0	0
T83	16640	0	0	0
T86	0	81	0	0
T87	0	241	0	0
T88	0	368	0	0
T89	0	223	0	0
T90	0	32	0	0
T113	0	33	0	0
T115	0	35	0	0
T116	0	14	0	0
T117	0	29	0	0