Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	592795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

355783

1

T1

1110

T2

1029

T3

349

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	506016	1			T1	1500		T2	1559		T3	467
values[0x0]	220691	1			T1	854		T2	651		T3	200
values[0x1]	221871	1			T1	846		T2	594		T3	221

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	497784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

450794

1

T1

1406

T2

1295

T3

435

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3544	1			T1	5		T2	5		T7	3
valid_sources[0x01]	3882	1			T1	13		T2	11		T7	5
valid_sources[0x02]	3151	1			T1	3		T2	8		T4	12
valid_sources[0x03]	6435	1			T1	23		T2	10		T4	1
valid_sources[0x04]	3532	1			T1	12		T2	6		T7	1
valid_sources[0x05]	3888	1			T1	4		T2	11		T4	3
valid_sources[0x06]	3420	1			T1	3		T7	2		T8	68
valid_sources[0x07]	6475	1			T1	10		T2	24		T4	5
valid_sources[0x08]	3513	1			T1	8		T2	19		T4	4
valid_sources[0x09]	3359	1			T1	11		T2	4		T4	2
valid_sources[0x0a]	7104	1			T1	25		T2	5		T4	9
valid_sources[0x0b]	3156	1			T1	25		T2	13		T7	3
valid_sources[0x0c]	3356	1			T2	1		T5	212		T7	5
valid_sources[0x0d]	3003	1			T1	18		T2	19		T7	5
valid_sources[0x0e]	3329	1			T1	4		T2	11		T7	3
valid_sources[0x0f]	3663	1			T1	13		T2	14		T4	2
valid_sources[0x10]	3209	1			T1	6		T2	8		T4	6
valid_sources[0x11]	3484	1			T1	4		T2	1		T7	10
valid_sources[0x12]	3211	1			T1	3		T2	10		T7	2
valid_sources[0x13]	3186	1			T1	18		T2	7		T7	5
valid_sources[0x14]	3587	1			T1	12		T2	1		T4	7
valid_sources[0x15]	3254	1			T1	1		T2	17		T7	4
valid_sources[0x16]	2957	1			T1	9		T2	16		T4	2
valid_sources[0x17]	3181	1			T1	6		T2	9		T4	1
valid_sources[0x18]	4201	1			T1	9		T2	2		T6	1
valid_sources[0x19]	2873	1			T1	21		T2	13		T7	3
valid_sources[0x1a]	4917	1			T2	10		T4	1		T7	3
valid_sources[0x1b]	3088	1			T1	5		T2	8		T6	7
valid_sources[0x1c]	2934	1			T1	4		T2	9		T7	4
valid_sources[0x1d]	3529	1			T1	8		T2	10		T7	3
valid_sources[0x1e]	3247	1			T1	16		T2	20		T7	4
valid_sources[0x1f]	3253	1			T1	5		T2	13		T4	2
valid_sources[0x20]	4257	1			T1	27		T2	10		T4	2
valid_sources[0x21]	2802	1			T1	4		T2	23		T7	2
valid_sources[0x22]	3953	1			T1	17		T2	15		T4	4
valid_sources[0x23]	3559	1			T2	8		T7	9		T8	68
valid_sources[0x24]	3197	1			T1	24		T2	9		T7	3
valid_sources[0x25]	3112	1			T1	1		T2	16		T7	3
valid_sources[0x26]	4033	1			T1	16		T2	4		T7	5
valid_sources[0x27]	4542	1			T1	14		T2	11		T7	4
valid_sources[0x28]	6322	1			T1	4		T2	14		T4	6
valid_sources[0x29]	2998	1			T1	13		T2	12		T4	2
valid_sources[0x2a]	5079	1			T1	7		T2	3		T7	3
valid_sources[0x2b]	3617	1			T1	5		T2	6		T7	5
valid_sources[0x2c]	3102	1			T1	33		T2	12		T4	3
valid_sources[0x2d]	3440	1			T1	5		T2	6		T4	1
valid_sources[0x2e]	2790	1			T1	12		T2	8		T4	2
valid_sources[0x2f]	3340	1			T1	8		T2	11		T7	2
valid_sources[0x30]	3401	1			T1	4		T2	15		T7	4
valid_sources[0x31]	8665	1			T1	6		T2	11		T7	2
valid_sources[0x32]	5939	1			T1	20		T2	13		T7	5
valid_sources[0x33]	3223	1			T1	20		T2	4		T7	8
valid_sources[0x34]	3312	1			T1	21		T2	7		T7	2
valid_sources[0x35]	3000	1			T1	2		T2	14		T4	1
valid_sources[0x36]	3218	1			T1	2		T2	13		T7	6
valid_sources[0x37]	3034	1			T1	16		T2	23		T4	2
valid_sources[0x38]	3104	1			T1	11		T2	13		T4	1
valid_sources[0x39]	3117	1			T1	21		T2	4		T4	3
valid_sources[0x3a]	3071	1			T1	15		T2	17		T4	1
valid_sources[0x3b]	6216	1			T1	1		T2	18		T4	1
valid_sources[0x3c]	3002	1			T1	55		T2	16		T4	6
valid_sources[0x3d]	3186	1			T1	9		T2	11		T4	2
valid_sources[0x3e]	3337	1			T1	14		T2	4		T4	2
valid_sources[0x3f]	3043	1			T1	30		T2	13		T4	1
valid_sources[0x40]	2969	1			T1	47		T2	10		T4	1
valid_sources[0x41]	3296	1			T1	33		T2	4		T7	5
valid_sources[0x42]	3863	1			T1	22		T2	8		T4	1
valid_sources[0x43]	2933	1			T1	4		T2	13		T4	4
valid_sources[0x44]	4662	1			T1	12		T2	15		T4	1
valid_sources[0x45]	3429	1			T1	25		T2	4		T7	2
valid_sources[0x46]	3614	1			T1	45		T2	6		T7	2
valid_sources[0x47]	3409	1			T1	12		T2	9		T7	8
valid_sources[0x48]	3640	1			T2	10		T7	2		T8	50
valid_sources[0x49]	3023	1			T1	9		T2	11		T7	3
valid_sources[0x4a]	3240	1			T2	12		T4	1		T7	3
valid_sources[0x4b]	3534	1			T1	6		T2	14		T4	3
valid_sources[0x4c]	4291	1			T1	6		T2	11		T4	1
valid_sources[0x4d]	3704	1			T1	10		T2	18		T7	1
valid_sources[0x4e]	3092	1			T1	8		T2	11		T7	4
valid_sources[0x4f]	3633	1			T2	15		T4	6		T7	5
valid_sources[0x50]	4147	1			T2	8		T7	4		T8	60
valid_sources[0x51]	3867	1			T1	2		T2	11		T7	2
valid_sources[0x52]	3756	1			T1	27		T2	8		T4	2
valid_sources[0x53]	3589	1			T1	6		T2	7		T7	3
valid_sources[0x54]	3239	1			T1	11		T2	20		T7	1
valid_sources[0x55]	4000	1			T1	19		T2	4		T4	2
valid_sources[0x56]	2842	1			T1	16		T2	7		T4	1
valid_sources[0x57]	3690	1			T1	16		T2	4		T4	2
valid_sources[0x58]	6587	1			T1	1		T2	11		T4	1
valid_sources[0x59]	3671	1			T2	4		T7	3		T8	52
valid_sources[0x5a]	3286	1			T1	12		T2	11		T7	1
valid_sources[0x5b]	3352	1			T1	12		T2	12		T4	4
valid_sources[0x5c]	3669	1			T1	4		T2	17		T4	2
valid_sources[0x5d]	3363	1			T1	8		T2	2		T4	1
valid_sources[0x5e]	3834	1			T1	11		T2	4		T4	1
valid_sources[0x5f]	3873	1			T1	2		T2	16		T4	2
valid_sources[0x60]	3033	1			T1	11		T2	10		T7	6
valid_sources[0x61]	2950	1			T1	9		T2	17		T7	2
valid_sources[0x62]	3481	1			T1	25		T2	22		T7	10
valid_sources[0x63]	3665	1			T1	14		T2	3		T6	1
valid_sources[0x64]	3014	1			T1	13		T2	23		T4	1
valid_sources[0x65]	3236	1			T1	3		T2	5		T7	6
valid_sources[0x66]	5335	1			T1	4		T2	8		T4	5
valid_sources[0x67]	3741	1			T1	7		T2	11		T4	3
valid_sources[0x68]	4257	1			T1	22		T2	7		T4	2
valid_sources[0x69]	3205	1			T1	8		T2	12		T4	3
valid_sources[0x6a]	4542	1			T1	3		T2	10		T7	1
valid_sources[0x6b]	3400	1			T1	22		T2	13		T7	5
valid_sources[0x6c]	3853	1			T1	26		T2	6		T4	4
valid_sources[0x6d]	3730	1			T1	4		T2	4		T7	1
valid_sources[0x6e]	3580	1			T1	3		T2	7		T4	1
valid_sources[0x6f]	3435	1			T1	10		T2	9		T4	2
valid_sources[0x70]	5557	1			T1	6		T2	18		T4	1
valid_sources[0x71]	3740	1			T1	4		T2	7		T7	2
valid_sources[0x72]	3085	1			T1	26		T2	14		T7	5
valid_sources[0x73]	3761	1			T1	11		T2	10		T4	3
valid_sources[0x74]	3711	1			T1	28		T2	8		T7	5
valid_sources[0x75]	4333	1			T1	15		T2	6		T3	888
valid_sources[0x76]	3469	1			T1	24		T2	12		T4	1
valid_sources[0x77]	3824	1			T1	6		T2	9		T7	3
valid_sources[0x78]	3412	1			T1	20		T2	13		T4	8
valid_sources[0x79]	3455	1			T1	1		T2	12		T4	2
valid_sources[0x7a]	3827	1			T2	20		T7	8		T8	65
valid_sources[0x7b]	3860	1			T1	2		T2	9		T4	4
valid_sources[0x7c]	3343	1			T1	5		T2	11		T7	4
valid_sources[0x7d]	4900	1			T1	8		T2	16		T7	5
valid_sources[0x7e]	3317	1			T1	18		T2	10		T4	1
valid_sources[0x7f]	3290	1			T1	21		T2	3		T4	9
valid_sources[0x80]	6900	1			T1	61		T2	8		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237707

1

T1

687

T2

711

T3

245

values[0x0]

all_enables

biggest_size

76969

1

T1

284

T2

212

T3

66

values[0x1]

all_enables

biggest_size

41107

1

T1

139

T2

106

T3

38