Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11431294	12643	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11431294	116754	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11431294	6764053	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11431294	186475	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11431294	12643	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11431294	116754	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11431294	6764053	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11431294	186475	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	12643	0	0
T1	26276	75	0	0
T2	35381	38	0	0
T3	7265	0	0	0
T4	5199	4	0	0
T5	3190	4	0	0
T6	1466	1	0	0
T7	3554	0	0	0
T8	98190	182	0	0
T9	3306	0	0	0
T10	31688	39	0	0
T11	0	4	0	0
T12	0	308	0	0
T24	0	136	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	116754	0	0
T1	26276	713	0	0
T2	35381	347	0	0
T3	7265	0	0	0
T4	5199	37	0	0
T5	3190	38	0	0
T6	1466	9	0	0
T7	3554	0	0	0
T8	98190	1656	0	0
T9	3306	0	0	0
T10	31688	355	0	0
T11	0	37	0	0
T12	0	2792	0	0
T24	0	1230	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	6764053	0	0
T1	26276	8709	0	0
T2	35381	27147	0	0
T3	7265	6696	0	0
T4	5199	4243	0	0
T5	3190	2273	0	0
T6	1466	831	0	0
T7	3554	2907	0	0
T8	98190	47700	0	0
T9	3306	710	0	0
T10	31688	25050	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	186475	0	0
T1	26276	1129	0	0
T2	35381	557	0	0
T3	7265	0	0	0
T4	5199	63	0	0
T5	3190	52	0	0
T6	1466	14	0	0
T7	3554	0	0	0
T8	98190	2669	0	0
T9	3306	0	0	0
T10	31688	590	0	0
T11	0	56	0	0
T12	0	4456	0	0
T24	0	1993	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	12643	0	0
T1	26276	75	0	0
T2	35381	38	0	0
T3	7265	0	0	0
T4	5199	4	0	0
T5	3190	4	0	0
T6	1466	1	0	0
T7	3554	0	0	0
T8	98190	182	0	0
T9	3306	0	0	0
T10	31688	39	0	0
T11	0	4	0	0
T12	0	308	0	0
T24	0	136	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	116754	0	0
T1	26276	713	0	0
T2	35381	347	0	0
T3	7265	0	0	0
T4	5199	37	0	0
T5	3190	38	0	0
T6	1466	9	0	0
T7	3554	0	0	0
T8	98190	1656	0	0
T9	3306	0	0	0
T10	31688	355	0	0
T11	0	37	0	0
T12	0	2792	0	0
T24	0	1230	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	6764053	0	0
T1	26276	8709	0	0
T2	35381	27147	0	0
T3	7265	6696	0	0
T4	5199	4243	0	0
T5	3190	2273	0	0
T6	1466	831	0	0
T7	3554	2907	0	0
T8	98190	47700	0	0
T9	3306	710	0	0
T10	31688	25050	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	186475	0	0
T1	26276	1129	0	0
T2	35381	557	0	0
T3	7265	0	0	0
T4	5199	63	0	0
T5	3190	52	0	0
T6	1466	14	0	0
T7	3554	0	0	0
T8	98190	2669	0	0
T9	3306	0	0	0
T10	31688	590	0	0
T11	0	56	0	0
T12	0	4456	0	0
T24	0	1993	0	0