Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T8,T10
1	0	Covered	T2,T8,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53666350	8612	0	0
CascadeEffAonToRstPorAboveRise_A	53666350	8612	0	0
CascadeEffAonToRstPorIoAboveFall_A	51518509	8612	0	0
CascadeEffAonToRstPorIoAboveRise_A	51518509	8612	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25760191	8612	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25760191	8612	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12879690	8612	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12879690	8612	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25760074	8612	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25760074	8612	0	0
CascadeLcToLcAboveFall_A	53666350	21255	0	0
CascadeLcToLcAboveRise_A	53666350	21255	0	0
CascadeLcToLcAonAboveFall_A	1625810	21255	0	0
CascadeLcToLcAonAboveRise_A	1625810	21255	0	0
CascadeLcToLcShadowedAboveFall_A	53666350	21255	0	0
CascadeLcToLcShadowedAboveRise_A	53666350	21255	0	0
CascadePorToAonAboveFall_A	1625810	6971	0	0
CascadeSysToSysAboveFall_A	53666350	21255	0	0
CascadeSysToSysAboveRise_A	53666350	21255	0	0
ScanRstToAonRise_A	1625810	198	0	0
StablePorToAonRise_A	1625810	8612	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11431294	21255	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11431294	21255	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11431294	21255	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11431294	21255	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12879690	21255	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12879690	21255	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11431294	21255	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11431294	21255	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11431294	21255	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11431294	21255	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	8612	0	0
T1	120765	27	0	0
T2	166481	18	0	0
T3	30653	1	0	0
T4	23080	2	0	0
T5	14488	2	0	0
T6	6497	1	0	0
T7	14888	1	0	0
T8	513028	110	0	0
T9	14155	2	0	0
T10	149123	14	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	8612	0	0
T1	120765	27	0	0
T2	166481	18	0	0
T3	30653	1	0	0
T4	23080	2	0	0
T5	14488	2	0	0
T6	6497	1	0	0
T7	14888	1	0	0
T8	513028	110	0	0
T9	14155	2	0	0
T10	149123	14	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51518509	8612	0	0
T1	115930	27	0	0
T2	159826	18	0	0
T3	29426	1	0	0
T4	22156	2	0	0
T5	13907	2	0	0
T6	6236	1	0	0
T7	14292	1	0	0
T8	492450	110	0	0
T9	13589	2	0	0
T10	143148	14	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51518509	8612	0	0
T1	115930	27	0	0
T2	159826	18	0	0
T3	29426	1	0	0
T4	22156	2	0	0
T5	13907	2	0	0
T6	6236	1	0	0
T7	14292	1	0	0
T8	492450	110	0	0
T9	13589	2	0	0
T10	143148	14	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760191	8612	0	0
T1	57970	27	0	0
T2	79914	18	0	0
T3	14713	1	0	0
T4	11079	2	0	0
T5	6955	2	0	0
T6	3117	1	0	0
T7	7146	1	0	0
T8	246271	110	0	0
T9	6795	2	0	0
T10	71580	14	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760191	8612	0	0
T1	57970	27	0	0
T2	79914	18	0	0
T3	14713	1	0	0
T4	11079	2	0	0
T5	6955	2	0	0
T6	3117	1	0	0
T7	7146	1	0	0
T8	246271	110	0	0
T9	6795	2	0	0
T10	71580	14	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	8612	0	0
T1	28985	27	0	0
T2	39958	18	0	0
T3	7355	1	0	0
T4	5539	2	0	0
T5	3476	2	0	0
T6	1559	1	0	0
T7	3572	1	0	0
T8	123121	110	0	0
T9	3397	2	0	0
T10	35791	14	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	8612	0	0
T1	28985	27	0	0
T2	39958	18	0	0
T3	7355	1	0	0
T4	5539	2	0	0
T5	3476	2	0	0
T6	1559	1	0	0
T7	3572	1	0	0
T8	123121	110	0	0
T9	3397	2	0	0
T10	35791	14	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760074	8612	0	0
T1	57975	27	0	0
T2	79919	18	0	0
T3	14713	1	0	0
T4	11078	2	0	0
T5	6953	2	0	0
T6	3118	1	0	0
T7	7146	1	0	0
T8	246257	110	0	0
T9	6795	2	0	0
T10	71579	14	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760074	8612	0	0
T1	57975	27	0	0
T2	79919	18	0	0
T3	14713	1	0	0
T4	11078	2	0	0
T5	6953	2	0	0
T6	3118	1	0	0
T7	7146	1	0	0
T8	246257	110	0	0
T9	6795	2	0	0
T10	71579	14	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	21255	0	0
T1	120765	102	0	0
T2	166481	56	0	0
T3	30653	1	0	0
T4	23080	6	0	0
T5	14488	6	0	0
T6	6497	2	0	0
T7	14888	1	0	0
T8	513028	292	0	0
T9	14155	2	0	0
T10	149123	53	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	21255	0	0
T1	120765	102	0	0
T2	166481	56	0	0
T3	30653	1	0	0
T4	23080	6	0	0
T5	14488	6	0	0
T6	6497	2	0	0
T7	14888	1	0	0
T8	513028	292	0	0
T9	14155	2	0	0
T10	149123	53	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	21255	0	0
T1	3637	102	0	0
T2	5092	56	0	0
T3	919	1	0	0
T4	691	6	0	0
T5	434	6	0	0
T6	193	2	0	0
T7	445	1	0	0
T8	15719	292	0	0
T9	423	2	0	0
T10	4536	53	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	21255	0	0
T1	3637	102	0	0
T2	5092	56	0	0
T3	919	1	0	0
T4	691	6	0	0
T5	434	6	0	0
T6	193	2	0	0
T7	445	1	0	0
T8	15719	292	0	0
T9	423	2	0	0
T10	4536	53	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	21255	0	0
T1	120765	102	0	0
T2	166481	56	0	0
T3	30653	1	0	0
T4	23080	6	0	0
T5	14488	6	0	0
T6	6497	2	0	0
T7	14888	1	0	0
T8	513028	292	0	0
T9	14155	2	0	0
T10	149123	53	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	21255	0	0
T1	120765	102	0	0
T2	166481	56	0	0
T3	30653	1	0	0
T4	23080	6	0	0
T5	14488	6	0	0
T6	6497	2	0	0
T7	14888	1	0	0
T8	513028	292	0	0
T9	14155	2	0	0
T10	149123	53	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	6971	0	0
T1	3637	27	0	0
T2	5092	8	0	0
T3	919	1	0	0
T4	691	1	0	0
T5	434	1	0	0
T6	193	1	0	0
T7	445	1	0	0
T8	15719	59	0	0
T9	423	10	0	0
T10	4536	7	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	21255	0	0
T1	120765	102	0	0
T2	166481	56	0	0
T3	30653	1	0	0
T4	23080	6	0	0
T5	14488	6	0	0
T6	6497	2	0	0
T7	14888	1	0	0
T8	513028	292	0	0
T9	14155	2	0	0
T10	149123	53	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53666350	21255	0	0
T1	120765	102	0	0
T2	166481	56	0	0
T3	30653	1	0	0
T4	23080	6	0	0
T5	14488	6	0	0
T6	6497	2	0	0
T7	14888	1	0	0
T8	513028	292	0	0
T9	14155	2	0	0
T10	149123	53	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	198	0	0
T2	5092	1	0	0
T3	919	0	0	0
T4	691	0	0	0
T5	434	0	0	0
T6	193	0	0	0
T7	445	0	0	0
T8	15719	7	0	0
T9	423	0	0	0
T10	4536	1	0	0
T12	0	9	0	0
T22	413	0	0	0
T24	0	3	0	0
T25	0	2	0	0
T27	0	1	0	0
T51	0	9	0	0
T55	0	1	0	0
T60	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	8612	0	0
T1	3637	27	0	0
T2	5092	18	0	0
T3	919	1	0	0
T4	691	2	0	0
T5	434	2	0	0
T6	193	1	0	0
T7	445	1	0	0
T8	15719	110	0	0
T9	423	2	0	0
T10	4536	14	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	21255	0	0
T1	28985	102	0	0
T2	39958	56	0	0
T3	7355	1	0	0
T4	5539	6	0	0
T5	3476	6	0	0
T6	1559	2	0	0
T7	3572	1	0	0
T8	123121	292	0	0
T9	3397	2	0	0
T10	35791	53	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	21255	0	0
T1	28985	102	0	0
T2	39958	56	0	0
T3	7355	1	0	0
T4	5539	6	0	0
T5	3476	6	0	0
T6	1559	2	0	0
T7	3572	1	0	0
T8	123121	292	0	0
T9	3397	2	0	0
T10	35791	53	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11431294	21255	0	0
T1	26276	102	0	0
T2	35381	56	0	0
T3	7265	1	0	0
T4	5199	6	0	0
T5	3190	6	0	0
T6	1466	2	0	0
T7	3554	1	0	0
T8	98190	292	0	0
T9	3306	2	0	0
T10	31688	53	0	0