Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12879690	13536	0	0
gen_assertions[0].RstEnOn_A	12879690	1078	0	0
gen_assertions[0].RstNOff_A	12879690	13536	0	0
gen_assertions[0].RstNOn_A	12879690	1078	0	0
gen_assertions[1].RstEnOff_A	51518509	12348	0	0
gen_assertions[1].RstEnOn_A	51518509	1016	0	0
gen_assertions[1].RstNOff_A	51518509	12348	0	0
gen_assertions[1].RstNOn_A	51518509	1016	0	0
gen_assertions[2].RstEnOff_A	25760191	12430	0	0
gen_assertions[2].RstEnOn_A	25760191	1050	0	0
gen_assertions[2].RstNOff_A	25760191	12430	0	0
gen_assertions[2].RstNOn_A	25760191	1050	0	0
gen_assertions[3].RstEnOff_A	25760074	12470	0	0
gen_assertions[3].RstEnOn_A	25760074	1085	0	0
gen_assertions[3].RstNOff_A	25760074	12470	0	0
gen_assertions[3].RstNOn_A	25760074	1085	0	0
gen_assertions[4].RstEnOff_A	1625810	20948	0	0
gen_assertions[4].RstEnOn_A	1625810	1108	0	0
gen_assertions[4].RstNOff_A	1625810	20948	0	0
gen_assertions[4].RstNOn_A	1625810	1108	0	0
gen_assertions[5].RstEnOff_A	12879690	13774	0	0
gen_assertions[5].RstEnOn_A	12879690	1171	0	0
gen_assertions[5].RstNOff_A	12879690	13774	0	0
gen_assertions[5].RstNOn_A	12879690	1171	0	0
gen_assertions[6].RstEnOff_A	12879690	13818	0	0
gen_assertions[6].RstEnOn_A	12879690	1214	0	0
gen_assertions[6].RstNOff_A	12879690	13818	0	0
gen_assertions[6].RstNOn_A	12879690	1214	0	0
gen_assertions[7].RstEnOff_A	12879690	13850	0	0
gen_assertions[7].RstEnOn_A	12879690	1242	0	0
gen_assertions[7].RstNOff_A	12879690	13850	0	0
gen_assertions[7].RstNOn_A	12879690	1242	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13536	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	2	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	4	0	0
T8	123121	197	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1078	0	0
T3	7355	2	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	4	0	0
T8	123121	15	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	1	0	0
T12	0	8	0	0
T22	3319	4	0	0
T24	0	12	0	0
T25	0	16	0	0
T51	0	18	0	0
T94	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13536	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	2	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	4	0	0
T8	123121	197	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1078	0	0
T3	7355	2	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	4	0	0
T8	123121	15	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	1	0	0
T12	0	8	0	0
T22	3319	4	0	0
T24	0	12	0	0
T25	0	16	0	0
T51	0	18	0	0
T94	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51518509	12348	0	0
T1	115930	67	0	0
T2	159826	35	0	0
T3	29426	5	0	0
T4	22156	5	0	0
T5	13907	2	0	0
T6	6236	1	0	0
T7	14292	7	0	0
T8	492450	180	0	0
T9	13589	0	0	0
T10	143148	36	0	0
T22	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51518509	1016	0	0
T3	29426	5	0	0
T4	22156	1	0	0
T5	13907	0	0	0
T6	6236	0	0	0
T7	14292	7	0	0
T8	492450	13	0	0
T9	13589	0	0	0
T10	143148	0	0	0
T11	19385	0	0	0
T12	0	6	0	0
T22	13285	4	0	0
T24	0	8	0	0
T25	0	19	0	0
T51	0	23	0	0
T61	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51518509	12348	0	0
T1	115930	67	0	0
T2	159826	35	0	0
T3	29426	5	0	0
T4	22156	5	0	0
T5	13907	2	0	0
T6	6236	1	0	0
T7	14292	7	0	0
T8	492450	180	0	0
T9	13589	0	0	0
T10	143148	36	0	0
T22	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51518509	1016	0	0
T3	29426	5	0	0
T4	22156	1	0	0
T5	13907	0	0	0
T6	6236	0	0	0
T7	14292	7	0	0
T8	492450	13	0	0
T9	13589	0	0	0
T10	143148	0	0	0
T11	19385	0	0	0
T12	0	6	0	0
T22	13285	4	0	0
T24	0	8	0	0
T25	0	19	0	0
T51	0	23	0	0
T61	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760191	12430	0	0
T1	57970	67	0	0
T2	79914	35	0	0
T3	14713	5	0	0
T4	11079	5	0	0
T5	6955	2	0	0
T6	3117	1	0	0
T7	7146	7	0	0
T8	246271	180	0	0
T9	6795	0	0	0
T10	71580	36	0	0
T22	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760191	1050	0	0
T3	14713	5	0	0
T4	11079	1	0	0
T5	6955	0	0	0
T6	3117	0	0	0
T7	7146	7	0	0
T8	246271	14	0	0
T9	6795	0	0	0
T10	71580	0	0	0
T11	9694	0	0	0
T12	0	8	0	0
T22	6641	7	0	0
T24	0	13	0	0
T25	0	20	0	0
T51	0	20	0	0
T61	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760191	12430	0	0
T1	57970	67	0	0
T2	79914	35	0	0
T3	14713	5	0	0
T4	11079	5	0	0
T5	6955	2	0	0
T6	3117	1	0	0
T7	7146	7	0	0
T8	246271	180	0	0
T9	6795	0	0	0
T10	71580	36	0	0
T22	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760191	1050	0	0
T3	14713	5	0	0
T4	11079	1	0	0
T5	6955	0	0	0
T6	3117	0	0	0
T7	7146	7	0	0
T8	246271	14	0	0
T9	6795	0	0	0
T10	71580	0	0	0
T11	9694	0	0	0
T12	0	8	0	0
T22	6641	7	0	0
T24	0	13	0	0
T25	0	20	0	0
T51	0	20	0	0
T61	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760074	12470	0	0
T1	57975	67	0	0
T2	79919	35	0	0
T3	14713	7	0	0
T4	11078	4	0	0
T5	6953	2	0	0
T6	3118	1	0	0
T7	7146	11	0	0
T8	246257	181	0	0
T9	6795	0	0	0
T10	71579	36	0	0
T22	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760074	1085	0	0
T3	14713	7	0	0
T4	11078	0	0	0
T5	6953	0	0	0
T6	3118	0	0	0
T7	7146	11	0	0
T8	246257	15	0	0
T9	6795	0	0	0
T10	71579	0	0	0
T11	9692	1	0	0
T12	0	7	0	0
T22	6642	7	0	0
T24	0	13	0	0
T25	0	18	0	0
T51	0	18	0	0
T61	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760074	12470	0	0
T1	57975	67	0	0
T2	79919	35	0	0
T3	14713	7	0	0
T4	11078	4	0	0
T5	6953	2	0	0
T6	3118	1	0	0
T7	7146	11	0	0
T8	246257	181	0	0
T9	6795	0	0	0
T10	71579	36	0	0
T22	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25760074	1085	0	0
T3	14713	7	0	0
T4	11078	0	0	0
T5	6953	0	0	0
T6	3118	0	0	0
T7	7146	11	0	0
T8	246257	15	0	0
T9	6795	0	0	0
T10	71579	0	0	0
T11	9692	1	0	0
T12	0	7	0	0
T22	6642	7	0	0
T24	0	13	0	0
T25	0	18	0	0
T51	0	18	0	0
T61	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	20948	0	0
T1	3637	76	0	0
T2	5092	56	0	0
T3	919	8	0	0
T4	691	6	0	0
T5	434	5	0	0
T6	193	2	0	0
T7	445	11	0	0
T8	15719	304	0	0
T9	423	2	0	0
T10	4536	53	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	1108	0	0
T3	919	7	0	0
T4	691	0	0	0
T5	434	0	0	0
T6	193	0	0	0
T7	445	10	0	0
T8	15719	15	0	0
T9	423	0	0	0
T10	4536	0	0	0
T11	605	0	0	0
T12	0	8	0	0
T22	413	9	0	0
T24	0	12	0	0
T25	0	20	0	0
T51	0	21	0	0
T57	0	5	0	0
T61	0	4	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	20948	0	0
T1	3637	76	0	0
T2	5092	56	0	0
T3	919	8	0	0
T4	691	6	0	0
T5	434	5	0	0
T6	193	2	0	0
T7	445	11	0	0
T8	15719	304	0	0
T9	423	2	0	0
T10	4536	53	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625810	1108	0	0
T3	919	7	0	0
T4	691	0	0	0
T5	434	0	0	0
T6	193	0	0	0
T7	445	10	0	0
T8	15719	15	0	0
T9	423	0	0	0
T10	4536	0	0	0
T11	605	0	0	0
T12	0	8	0	0
T22	413	9	0	0
T24	0	12	0	0
T25	0	20	0	0
T51	0	21	0	0
T57	0	5	0	0
T61	0	4	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13774	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	7	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	11	0	0
T8	123121	194	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	8	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1171	0	0
T3	7355	7	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	11	0	0
T8	123121	14	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	0	0	0
T12	0	8	0	0
T22	3319	8	0	0
T24	0	14	0	0
T25	0	19	0	0
T51	0	22	0	0
T57	0	6	0	0
T61	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13774	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	7	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	11	0	0
T8	123121	194	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	8	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1171	0	0
T3	7355	7	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	11	0	0
T8	123121	14	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	0	0	0
T12	0	8	0	0
T22	3319	8	0	0
T24	0	14	0	0
T25	0	19	0	0
T51	0	22	0	0
T57	0	6	0	0
T61	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13818	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	10	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	14	0	0
T8	123121	193	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	11	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1214	0	0
T3	7355	10	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	14	0	0
T8	123121	12	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	1	0	0
T12	0	8	0	0
T22	3319	11	0	0
T24	0	13	0	0
T25	0	20	0	0
T51	0	16	0	0
T61	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13818	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	10	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	14	0	0
T8	123121	193	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	11	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1214	0	0
T3	7355	10	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	14	0	0
T8	123121	12	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	1	0	0
T12	0	8	0	0
T22	3319	11	0	0
T24	0	13	0	0
T25	0	20	0	0
T51	0	16	0	0
T61	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13850	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	10	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	14	0	0
T8	123121	197	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	12	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1242	0	0
T3	7355	10	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	14	0	0
T8	123121	17	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	0	0	0
T12	0	6	0	0
T22	3319	12	0	0
T24	0	13	0	0
T25	0	15	0	0
T51	0	19	0	0
T52	0	1	0	0
T61	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	13850	0	0
T1	28985	75	0	0
T2	39958	38	0	0
T3	7355	10	0	0
T4	5539	4	0	0
T5	3476	4	0	0
T6	1559	1	0	0
T7	3572	14	0	0
T8	123121	197	0	0
T9	3397	0	0	0
T10	35791	39	0	0
T22	0	12	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12879690	1242	0	0
T3	7355	10	0	0
T4	5539	0	0	0
T5	3476	0	0	0
T6	1559	0	0	0
T7	3572	14	0	0
T8	123121	17	0	0
T9	3397	0	0	0
T10	35791	0	0	0
T11	4847	0	0	0
T12	0	6	0	0
T22	3319	12	0	0
T24	0	13	0	0
T25	0	15	0	0
T51	0	19	0	0
T52	0	1	0	0
T61	0	7	0	0