Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12212423	7163	0	0
alert_regwen_rd_A	12212423	4920	0	0
cpu_regwen_rd_A	12212423	5035	0	0
sw_rst_ctrl_n_0_rd_A	12212423	11277	0	0
sw_rst_ctrl_n_1_rd_A	12212423	11437	0	0
sw_rst_ctrl_n_2_rd_A	12212423	11462	0	0
sw_rst_ctrl_n_3_rd_A	12212423	10818	0	0
sw_rst_ctrl_n_4_rd_A	12212423	11272	0	0
sw_rst_ctrl_n_5_rd_A	12212423	11542	0	0
sw_rst_ctrl_n_6_rd_A	12212423	11181	0	0
sw_rst_ctrl_n_7_rd_A	12212423	11411	0	0
sw_rst_regwen_0_rd_A	12212423	5889	0	0
sw_rst_regwen_1_rd_A	12212423	5869	0	0
sw_rst_regwen_2_rd_A	12212423	5767	0	0
sw_rst_regwen_3_rd_A	12212423	6043	0	0
sw_rst_regwen_4_rd_A	12212423	5778	0	0
sw_rst_regwen_5_rd_A	12212423	6050	0	0
sw_rst_regwen_6_rd_A	12212423	6050	0	0
sw_rst_regwen_7_rd_A	12212423	5798	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	7163	0	0
T70	11223	1	0	0
T71	20949	4	0	0
T72	3347	154	0	0
T73	6425	271	0	0
T74	12607	615	0	0
T80	4154	6	0	0
T95	26757	2	0	0
T96	2949	12	0	0
T97	20685	2	0	0
T119	18344	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	4920	0	0
T2	35381	26	0	0
T3	7265	0	0	0
T4	5199	0	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	8	0	0
T22	3230	0	0	0
T24	0	157	0	0
T25	0	118	0	0
T56	0	48	0	0
T102	0	45	0	0
T106	0	260	0	0
T129	0	88	0	0
T130	0	263	0	0
T131	0	50	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	5035	0	0
T2	35381	35	0	0
T3	7265	0	0	0
T4	5199	0	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	23	0	0
T22	3230	0	0	0
T24	0	194	0	0
T25	0	121	0	0
T56	0	50	0	0
T102	0	55	0	0
T106	0	293	0	0
T129	0	64	0	0
T130	0	214	0	0
T131	0	77	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11277	0	0
T2	35381	31	0	0
T3	7265	0	0	0
T4	5199	8	0	0
T5	3190	0	0	0
T6	1466	4	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	31	0	0
T22	3230	0	0	0
T24	0	367	0	0
T25	0	350	0	0
T54	0	13	0	0
T94	0	82	0	0
T102	0	56	0	0
T132	0	46	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11437	0	0
T2	35381	36	0	0
T3	7265	0	0	0
T4	5199	2	0	0
T5	3190	0	0	0
T6	1466	3	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	29	0	0
T22	3230	0	0	0
T24	0	324	0	0
T25	0	390	0	0
T54	0	17	0	0
T94	0	68	0	0
T102	0	62	0	0
T132	0	41	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11462	0	0
T2	35381	32	0	0
T3	7265	0	0	0
T4	5199	11	0	0
T5	3190	0	0	0
T6	1466	2	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	21	0	0
T22	3230	0	0	0
T24	0	351	0	0
T25	0	399	0	0
T54	0	15	0	0
T94	0	66	0	0
T102	0	46	0	0
T132	0	48	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	10818	0	0
T2	35381	31	0	0
T3	7265	0	0	0
T4	5199	14	0	0
T5	3190	0	0	0
T6	1466	4	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	31	0	0
T22	3230	0	0	0
T24	0	317	0	0
T25	0	349	0	0
T54	0	5	0	0
T94	0	67	0	0
T102	0	70	0	0
T132	0	40	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11272	0	0
T2	35381	29	0	0
T3	7265	0	0	0
T4	5199	12	0	0
T5	3190	0	0	0
T6	1466	1	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	17	0	0
T22	3230	0	0	0
T24	0	392	0	0
T25	0	345	0	0
T54	0	8	0	0
T94	0	56	0	0
T102	0	50	0	0
T132	0	30	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11542	0	0
T2	35381	23	0	0
T3	7265	0	0	0
T4	5199	16	0	0
T5	3190	0	0	0
T6	1466	8	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	16	0	0
T22	3230	0	0	0
T24	0	366	0	0
T25	0	351	0	0
T56	0	48	0	0
T94	0	70	0	0
T102	0	64	0	0
T132	0	48	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11181	0	0
T2	35381	28	0	0
T3	7265	0	0	0
T4	5199	15	0	0
T5	3190	0	0	0
T6	1466	6	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	11	0	0
T22	3230	0	0	0
T24	0	331	0	0
T25	0	348	0	0
T54	0	1	0	0
T94	0	65	0	0
T102	0	65	0	0
T132	0	41	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	11411	0	0
T2	35381	53	0	0
T3	7265	0	0	0
T4	5199	3	0	0
T5	3190	0	0	0
T6	1466	7	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	36	0	0
T22	3230	0	0	0
T24	0	405	0	0
T25	0	364	0	0
T54	0	12	0	0
T94	0	77	0	0
T102	0	58	0	0
T132	0	27	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	5889	0	0
T2	35381	54	0	0
T3	7265	0	0	0
T4	5199	7	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	25	0	0
T22	3230	0	0	0
T24	0	176	0	0
T25	0	127	0	0
T39	0	20	0	0
T41	0	2	0	0
T56	0	36	0	0
T102	0	71	0	0
T133	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	5869	0	0
T2	35381	37	0	0
T3	7265	0	0	0
T4	5199	4	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	19	0	0
T22	3230	0	0	0
T24	0	229	0	0
T25	0	138	0	0
T39	0	33	0	0
T41	0	4	0	0
T54	0	10	0	0
T56	0	44	0	0
T102	0	52	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	5767	0	0
T2	35381	36	0	0
T3	7265	0	0	0
T4	5199	0	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	37	0	0
T22	3230	0	0	0
T24	0	226	0	0
T25	0	116	0	0
T39	0	15	0	0
T41	0	8	0	0
T54	0	7	0	0
T56	0	50	0	0
T102	0	56	0	0
T133	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	6043	0	0
T2	35381	44	0	0
T3	7265	0	0	0
T4	5199	0	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	29	0	0
T22	3230	0	0	0
T24	0	238	0	0
T25	0	109	0	0
T39	0	29	0	0
T41	0	2	0	0
T54	0	8	0	0
T56	0	56	0	0
T102	0	62	0	0
T133	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	5778	0	0
T2	35381	42	0	0
T3	7265	0	0	0
T4	5199	4	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	22	0	0
T22	3230	0	0	0
T24	0	203	0	0
T25	0	132	0	0
T39	0	30	0	0
T41	0	1	0	0
T54	0	5	0	0
T56	0	62	0	0
T102	0	39	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	6050	0	0
T2	35381	13	0	0
T3	7265	0	0	0
T4	5199	8	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	13	0	0
T22	3230	0	0	0
T24	0	203	0	0
T25	0	127	0	0
T39	0	54	0	0
T41	0	2	0	0
T56	0	48	0	0
T102	0	52	0	0
T133	0	9	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	6050	0	0
T2	35381	24	0	0
T3	7265	0	0	0
T4	5199	7	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	44	0	0
T22	3230	0	0	0
T24	0	157	0	0
T25	0	145	0	0
T39	0	23	0	0
T41	0	7	0	0
T54	0	9	0	0
T56	0	47	0	0
T102	0	79	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212423	5798	0	0
T2	35381	55	0	0
T3	7265	0	0	0
T4	5199	0	0	0
T5	3190	0	0	0
T6	1466	0	0	0
T7	3554	0	0	0
T8	98190	0	0	0
T9	3306	0	0	0
T10	31688	16	0	0
T22	3230	0	0	0
T24	0	181	0	0
T25	0	94	0	0
T39	0	41	0	0
T41	0	7	0	0
T54	0	4	0	0
T56	0	38	0	0
T102	0	61	0	0
T133	0	1	0	0