RSTMGR Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.630s 261.791us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.960s 128.455us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.940s 85.457us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.510s 2.280ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.720s 435.786us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.980s 197.196us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.940s 85.457us 20 20 100.00
rstmgr_csr_aliasing 2.720s 435.786us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.980s 228.023us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.660s 531.208us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.570s 269.916us 50 50 100.00
V2 reset_info rstmgr_reset 7.730s 1.946ms 50 50 100.00
V2 cpu_info rstmgr_reset 7.730s 1.946ms 50 50 100.00
V2 alert_info rstmgr_reset 7.730s 1.946ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 7.730s 1.946ms 50 50 100.00
V2 stress_all rstmgr_stress_all 52.500s 16.162ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.890s 83.537us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.920s 623.917us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.920s 623.917us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.960s 128.455us 5 5 100.00
rstmgr_csr_rw 0.940s 85.457us 20 20 100.00
rstmgr_csr_aliasing 2.720s 435.786us 5 5 100.00
rstmgr_same_csr_outstanding 1.650s 285.824us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.960s 128.455us 5 5 100.00
rstmgr_csr_rw 0.940s 85.457us 20 20 100.00
rstmgr_csr_aliasing 2.720s 435.786us 5 5 100.00
rstmgr_same_csr_outstanding 1.650s 285.824us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 25.990s 16.703ms 5 5 100.00
rstmgr_tl_intg_err 3.250s 920.921us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 25.990s 16.703ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 25.990s 16.703ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.250s 920.921us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.250s 171.901us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.800s 2.351ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.150s 243.992us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 25.990s 16.703ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.940s 85.457us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.940s 85.457us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Past Results