RSTMGR Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.640s 259.750us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.040s 142.359us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.910s 74.152us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 5.820s 488.532us 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.250s 355.700us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.940s 188.531us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.910s 74.152us 20 20 100.00
rstmgr_csr_aliasing 2.250s 355.700us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.020s 224.361us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.750s 463.324us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.620s 302.862us 50 50 100.00
V2 reset_info rstmgr_reset 8.450s 1.982ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.450s 1.982ms 50 50 100.00
V2 alert_info rstmgr_reset 8.450s 1.982ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.450s 1.982ms 50 50 100.00
V2 stress_all rstmgr_stress_all 51.090s 14.399ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.060s 87.075us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.900s 494.655us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.900s 494.655us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.040s 142.359us 5 5 100.00
rstmgr_csr_rw 0.910s 74.152us 20 20 100.00
rstmgr_csr_aliasing 2.250s 355.700us 5 5 100.00
rstmgr_same_csr_outstanding 1.740s 289.666us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.040s 142.359us 5 5 100.00
rstmgr_csr_rw 0.910s 74.152us 20 20 100.00
rstmgr_csr_aliasing 2.250s 355.700us 5 5 100.00
rstmgr_same_csr_outstanding 1.740s 289.666us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 28.460s 16.513ms 5 5 100.00
rstmgr_tl_intg_err 3.590s 922.912us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 28.460s 16.513ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 28.460s 16.513ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.590s 922.912us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.330s 176.403us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.250s 2.358ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.210s 244.328us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 28.460s 16.513ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.910s 74.152us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.910s 74.152us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.87 -- 99.83 99.46 98.77

Past Results