RSTMGR Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.620s 249.500us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.020s 148.327us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.940s 91.540us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.740s 1.561ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.550s 357.747us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.800s 178.409us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.940s 91.540us 20 20 100.00
rstmgr_csr_aliasing 2.550s 357.747us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.040s 192.737us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.030s 547.612us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.610s 304.942us 50 50 100.00
V2 reset_info rstmgr_reset 7.650s 1.804ms 50 50 100.00
V2 cpu_info rstmgr_reset 7.650s 1.804ms 50 50 100.00
V2 alert_info rstmgr_reset 7.650s 1.804ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 7.650s 1.804ms 50 50 100.00
V2 stress_all rstmgr_stress_all 55.120s 14.769ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.860s 89.691us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.870s 578.199us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.870s 578.199us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.020s 148.327us 5 5 100.00
rstmgr_csr_rw 0.940s 91.540us 20 20 100.00
rstmgr_csr_aliasing 2.550s 357.747us 5 5 100.00
rstmgr_same_csr_outstanding 1.700s 259.279us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.020s 148.327us 5 5 100.00
rstmgr_csr_rw 0.940s 91.540us 20 20 100.00
rstmgr_csr_aliasing 2.550s 357.747us 5 5 100.00
rstmgr_same_csr_outstanding 1.700s 259.279us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 26.760s 16.553ms 5 5 100.00
rstmgr_tl_intg_err 3.400s 937.413us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 26.760s 16.553ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 26.760s 16.553ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.400s 937.413us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.280s 179.439us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.370s 2.352ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.220s 244.792us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 26.760s 16.553ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.940s 91.540us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.940s 91.540us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Past Results