Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	587281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

353841

1

T1

40

T2

1135

T6

1057

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	500937	1			T1	63		T2	1500		T4	1
values[0x0]	219584	1			T1	29		T2	897		T6	820
values[0x1]	220601	1			T1	36		T2	803		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	492939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

448183

1

T1

54

T2

1446

T6

1396

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3199	1			T9	7		T10	12		T11	84
valid_sources[0x01]	3420	1			T9	9		T10	6		T11	97
valid_sources[0x02]	3164	1			T9	13		T10	7		T11	79
valid_sources[0x03]	5801	1			T9	5		T10	19		T11	64
valid_sources[0x04]	4992	1			T9	4		T10	3		T11	85
valid_sources[0x05]	3139	1			T9	4		T10	13		T11	94
valid_sources[0x06]	3742	1			T9	14		T10	7		T11	72
valid_sources[0x07]	3507	1			T9	7		T10	9		T11	103
valid_sources[0x08]	3922	1			T9	10		T10	32		T11	83
valid_sources[0x09]	3919	1			T9	9		T10	5		T11	76
valid_sources[0x0a]	4336	1			T9	15		T10	10		T11	85
valid_sources[0x0b]	2848	1			T9	9		T10	22		T11	88
valid_sources[0x0c]	3192	1			T9	15		T10	15		T11	73
valid_sources[0x0d]	4198	1			T9	18		T10	11		T11	87
valid_sources[0x0e]	2881	1			T9	22		T10	16		T11	89
valid_sources[0x0f]	2682	1			T9	9		T10	7		T11	93
valid_sources[0x10]	3612	1			T9	17		T10	10		T11	85
valid_sources[0x11]	2988	1			T9	10		T10	10		T11	93
valid_sources[0x12]	4125	1			T9	15		T10	8		T11	75
valid_sources[0x13]	3142	1			T9	8		T10	14		T11	82
valid_sources[0x14]	4303	1			T9	11		T10	10		T11	84
valid_sources[0x15]	4109	1			T9	4		T10	7		T11	104
valid_sources[0x16]	3350	1			T9	5		T10	13		T11	90
valid_sources[0x17]	3314	1			T9	8		T10	10		T11	91
valid_sources[0x18]	3028	1			T9	6		T10	13		T11	72
valid_sources[0x19]	3102	1			T9	9		T10	15		T11	74
valid_sources[0x1a]	3287	1			T9	5		T10	21		T11	94
valid_sources[0x1b]	3169	1			T9	7		T10	14		T11	80
valid_sources[0x1c]	3267	1			T9	12		T10	20		T11	97
valid_sources[0x1d]	3484	1			T9	7		T10	15		T11	60
valid_sources[0x1e]	3265	1			T9	11		T10	21		T11	85
valid_sources[0x1f]	3118	1			T9	7		T10	17		T11	79
valid_sources[0x20]	3316	1			T9	15		T10	22		T11	84
valid_sources[0x21]	3510	1			T9	6		T10	13		T11	77
valid_sources[0x22]	3650	1			T9	8		T10	15		T11	74
valid_sources[0x23]	3232	1			T9	13		T10	8		T11	81
valid_sources[0x24]	2762	1			T9	12		T10	18		T11	84
valid_sources[0x25]	2997	1			T9	8		T10	11		T11	99
valid_sources[0x26]	2886	1			T9	6		T10	20		T11	83
valid_sources[0x27]	3325	1			T9	17		T10	23		T11	69
valid_sources[0x28]	4712	1			T9	4		T10	10		T11	109
valid_sources[0x29]	7096	1			T9	11		T10	15		T11	81
valid_sources[0x2a]	3493	1			T9	8		T10	18		T11	89
valid_sources[0x2b]	3296	1			T9	7		T10	15		T11	78
valid_sources[0x2c]	3608	1			T9	9		T10	17		T11	68
valid_sources[0x2d]	3413	1			T4	1		T9	4		T10	10
valid_sources[0x2e]	3279	1			T9	8		T10	7		T11	81
valid_sources[0x2f]	2758	1			T9	4		T10	15		T11	70
valid_sources[0x30]	3734	1			T9	12		T10	12		T11	68
valid_sources[0x31]	3196	1			T9	7		T10	6		T11	67
valid_sources[0x32]	3057	1			T9	13		T10	9		T11	66
valid_sources[0x33]	4320	1			T9	1		T10	15		T11	94
valid_sources[0x34]	3651	1			T9	22		T10	15		T11	67
valid_sources[0x35]	3181	1			T9	3		T10	22		T11	72
valid_sources[0x36]	3073	1			T9	9		T10	20		T11	83
valid_sources[0x37]	3846	1			T9	9		T10	12		T11	69
valid_sources[0x38]	3191	1			T9	10		T10	3		T11	79
valid_sources[0x39]	3657	1			T9	7		T10	13		T11	78
valid_sources[0x3a]	3650	1			T9	11		T10	10		T11	73
valid_sources[0x3b]	6960	1			T9	8		T10	18		T11	85
valid_sources[0x3c]	3776	1			T9	7		T10	18		T11	91
valid_sources[0x3d]	3796	1			T9	3		T10	20		T11	52
valid_sources[0x3e]	3424	1			T9	9		T10	13		T11	85
valid_sources[0x3f]	3073	1			T9	11		T10	23		T11	81
valid_sources[0x40]	3597	1			T9	15		T10	8		T11	70
valid_sources[0x41]	4328	1			T9	9		T10	23		T11	85
valid_sources[0x42]	3989	1			T3	3		T9	12		T10	7
valid_sources[0x43]	3439	1			T9	6		T10	8		T11	80
valid_sources[0x44]	3258	1			T9	4		T10	12		T11	93
valid_sources[0x45]	3427	1			T9	19		T10	13		T11	94
valid_sources[0x46]	3072	1			T9	6		T10	9		T11	74
valid_sources[0x47]	3122	1			T9	13		T10	14		T11	83
valid_sources[0x48]	3797	1			T9	12		T10	8		T11	76
valid_sources[0x49]	3829	1			T9	7		T10	13		T11	82
valid_sources[0x4a]	3243	1			T9	11		T10	5		T11	85
valid_sources[0x4b]	3352	1			T9	7		T10	6		T11	104
valid_sources[0x4c]	2798	1			T9	16		T10	10		T11	58
valid_sources[0x4d]	3976	1			T9	8		T10	11		T11	78
valid_sources[0x4e]	3636	1			T9	6		T10	11		T11	66
valid_sources[0x4f]	3493	1			T9	17		T10	11		T11	77
valid_sources[0x50]	6614	1			T9	10		T10	10		T11	84
valid_sources[0x51]	3580	1			T9	8		T10	12		T11	64
valid_sources[0x52]	3392	1			T9	8		T10	10		T11	91
valid_sources[0x53]	3627	1			T9	18		T10	15		T11	74
valid_sources[0x54]	2844	1			T9	3		T10	30		T11	58
valid_sources[0x55]	2779	1			T9	14		T10	14		T11	70
valid_sources[0x56]	3327	1			T9	9		T10	9		T11	89
valid_sources[0x57]	3142	1			T9	9		T10	7		T11	83
valid_sources[0x58]	3694	1			T9	4		T10	11		T11	88
valid_sources[0x59]	3020	1			T9	9		T10	2		T11	74
valid_sources[0x5a]	2928	1			T9	8		T10	13		T11	63
valid_sources[0x5b]	3254	1			T9	6		T10	21		T11	60
valid_sources[0x5c]	3240	1			T9	13		T10	10		T11	75
valid_sources[0x5d]	3803	1			T9	3		T10	22		T11	74
valid_sources[0x5e]	4004	1			T9	14		T10	16		T11	84
valid_sources[0x5f]	3427	1			T9	11		T10	9		T11	91
valid_sources[0x60]	3867	1			T9	12		T10	9		T11	89
valid_sources[0x61]	3210	1			T9	14		T10	12		T11	75
valid_sources[0x62]	2837	1			T9	4		T10	11		T11	90
valid_sources[0x63]	3556	1			T9	12		T10	7		T11	88
valid_sources[0x64]	3137	1			T9	6		T10	9		T11	94
valid_sources[0x65]	3154	1			T9	3		T10	6		T11	76
valid_sources[0x66]	6480	1			T6	3200		T9	6		T10	9
valid_sources[0x67]	4149	1			T9	4		T10	7		T11	99
valid_sources[0x68]	3478	1			T9	5		T10	6		T11	82
valid_sources[0x69]	3473	1			T9	10		T10	10		T11	77
valid_sources[0x6a]	3492	1			T9	15		T10	12		T11	76
valid_sources[0x6b]	4655	1			T9	5		T10	11		T11	80
valid_sources[0x6c]	3902	1			T9	4		T10	6		T11	82
valid_sources[0x6d]	2905	1			T9	7		T10	4		T11	92
valid_sources[0x6e]	3922	1			T9	6		T10	11		T11	75
valid_sources[0x6f]	3669	1			T9	12		T10	9		T11	83
valid_sources[0x70]	2812	1			T9	13		T10	24		T11	81
valid_sources[0x71]	3966	1			T9	11		T10	18		T11	70
valid_sources[0x72]	2926	1			T9	10		T10	19		T11	87
valid_sources[0x73]	5104	1			T9	17		T10	15		T11	80
valid_sources[0x74]	3843	1			T9	15		T10	8		T11	77
valid_sources[0x75]	3181	1			T9	6		T10	4		T11	66
valid_sources[0x76]	6591	1			T9	10		T10	15		T11	69
valid_sources[0x77]	3185	1			T9	5		T10	12		T11	76
valid_sources[0x78]	3576	1			T9	9		T10	10		T11	72
valid_sources[0x79]	2704	1			T9	7		T10	8		T11	81
valid_sources[0x7a]	3542	1			T9	4		T10	10		T11	87
valid_sources[0x7b]	3493	1			T9	2		T10	1		T11	69
valid_sources[0x7c]	3674	1			T9	12		T10	15		T11	87
valid_sources[0x7d]	4331	1			T9	8		T10	16		T11	91
valid_sources[0x7e]	3070	1			T9	9		T10	13		T11	99
valid_sources[0x7f]	2988	1			T9	5		T10	9		T11	78
valid_sources[0x80]	3902	1			T9	10		T10	11		T11	78

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

234976

1

T1

26

T2

688

T6

650

values[0x0]

all_enables

biggest_size

77260

1

T1

9

T2

309

T6

254

values[0x1]

all_enables

biggest_size

41605

1

T1

5

T2

138

T6

153