Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T9,T11,T22
1	0	Covered	T9,T11,T37

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T9,T11,T12
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52245747	8832	0	0
CascadeEffAonToRstPorAboveRise_A	52245747	8832	0	0
CascadeEffAonToRstPorIoAboveFall_A	50154887	8832	0	0
CascadeEffAonToRstPorIoAboveRise_A	50154887	8832	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25078022	8832	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25078022	8832	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12538562	8832	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12538562	8832	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25078098	8832	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25078098	8832	0	0
CascadeLcToLcAboveFall_A	52245747	21426	0	0
CascadeLcToLcAboveRise_A	52245747	21426	0	0
CascadeLcToLcAonAboveFall_A	1583728	21426	0	0
CascadeLcToLcAonAboveRise_A	1583728	21426	0	0
CascadeLcToLcShadowedAboveFall_A	52245747	21426	0	0
CascadeLcToLcShadowedAboveRise_A	52245747	21426	0	0
CascadePorToAonAboveFall_A	1583728	7152	0	0
CascadeSysToSysAboveFall_A	52245747	21426	0	0
CascadeSysToSysAboveRise_A	52245747	21426	0	0
ScanRstToAonRise_A	1583728	219	0	0
StablePorToAonRise_A	1583728	8832	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11125207	21426	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11125207	21426	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11125207	21426	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11125207	21426	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12538562	21426	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12538562	21426	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11125207	21426	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11125207	21426	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11125207	21426	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11125207	21426	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	8832	0	0
T1	13267	1	0	0
T2	216682	27	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	27	0	0
T7	36400	1	0	0
T8	10510	1	0	0
T9	144553	17	0	0
T10	187791	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	8832	0	0
T1	13267	1	0	0
T2	216682	27	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	27	0	0
T7	36400	1	0	0
T8	10510	1	0	0
T9	144553	17	0	0
T10	187791	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50154887	8832	0	0
T1	12737	1	0	0
T2	207990	27	0	0
T3	6092	1	0	0
T4	19327	2	0	0
T5	13320	2	0	0
T6	181043	27	0	0
T7	34943	1	0	0
T8	10089	1	0	0
T9	138767	17	0	0
T10	180275	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50154887	8832	0	0
T1	12737	1	0	0
T2	207990	27	0	0
T3	6092	1	0	0
T4	19327	2	0	0
T5	13320	2	0	0
T6	181043	27	0	0
T7	34943	1	0	0
T8	10089	1	0	0
T9	138767	17	0	0
T10	180275	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078022	8832	0	0
T1	6369	1	0	0
T2	103998	27	0	0
T3	3046	1	0	0
T4	9664	2	0	0
T5	6659	2	0	0
T6	90502	27	0	0
T7	17472	1	0	0
T8	5043	1	0	0
T9	69384	17	0	0
T10	90138	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078022	8832	0	0
T1	6369	1	0	0
T2	103998	27	0	0
T3	3046	1	0	0
T4	9664	2	0	0
T5	6659	2	0	0
T6	90502	27	0	0
T7	17472	1	0	0
T8	5043	1	0	0
T9	69384	17	0	0
T10	90138	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	8832	0	0
T1	3183	1	0	0
T2	52001	27	0	0
T3	1522	1	0	0
T4	4831	2	0	0
T5	3329	2	0	0
T6	45242	27	0	0
T7	8735	1	0	0
T8	2520	1	0	0
T9	34696	17	0	0
T10	45066	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	8832	0	0
T1	3183	1	0	0
T2	52001	27	0	0
T3	1522	1	0	0
T4	4831	2	0	0
T5	3329	2	0	0
T6	45242	27	0	0
T7	8735	1	0	0
T8	2520	1	0	0
T9	34696	17	0	0
T10	45066	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078098	8832	0	0
T1	6368	1	0	0
T2	104008	27	0	0
T3	3045	1	0	0
T4	9664	2	0	0
T5	6660	2	0	0
T6	90537	27	0	0
T7	17472	1	0	0
T8	5043	1	0	0
T9	69386	17	0	0
T10	90134	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078098	8832	0	0
T1	6368	1	0	0
T2	104008	27	0	0
T3	3045	1	0	0
T4	9664	2	0	0
T5	6660	2	0	0
T6	90537	27	0	0
T7	17472	1	0	0
T8	5043	1	0	0
T9	69386	17	0	0
T10	90134	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	21426	0	0
T1	13267	8	0	0
T2	216682	102	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	102	0	0
T7	36400	1	0	0
T8	10510	8	0	0
T9	144553	47	0	0
T10	187791	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	21426	0	0
T1	13267	8	0	0
T2	216682	102	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	102	0	0
T7	36400	1	0	0
T8	10510	8	0	0
T9	144553	47	0	0
T10	187791	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	21426	0	0
T1	396	8	0	0
T2	6515	102	0	0
T3	189	1	0	0
T4	602	2	0	0
T5	414	2	0	0
T6	5672	102	0	0
T7	1090	1	0	0
T8	314	8	0	0
T9	4410	47	0	0
T10	5647	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	21426	0	0
T1	396	8	0	0
T2	6515	102	0	0
T3	189	1	0	0
T4	602	2	0	0
T5	414	2	0	0
T6	5672	102	0	0
T7	1090	1	0	0
T8	314	8	0	0
T9	4410	47	0	0
T10	5647	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	21426	0	0
T1	13267	8	0	0
T2	216682	102	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	102	0	0
T7	36400	1	0	0
T8	10510	8	0	0
T9	144553	47	0	0
T10	187791	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	21426	0	0
T1	13267	8	0	0
T2	216682	102	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	102	0	0
T7	36400	1	0	0
T8	10510	8	0	0
T9	144553	47	0	0
T10	187791	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	7152	0	0
T1	396	1	0	0
T2	6515	27	0	0
T3	189	1	0	0
T4	602	16	0	0
T5	414	9	0	0
T6	5672	27	0	0
T7	1090	1	0	0
T8	314	1	0	0
T9	4410	10	0	0
T10	5647	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	21426	0	0
T1	13267	8	0	0
T2	216682	102	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	102	0	0
T7	36400	1	0	0
T8	10510	8	0	0
T9	144553	47	0	0
T10	187791	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52245747	21426	0	0
T1	13267	8	0	0
T2	216682	102	0	0
T3	6346	1	0	0
T4	20134	2	0	0
T5	13876	2	0	0
T6	188560	102	0	0
T7	36400	1	0	0
T8	10510	8	0	0
T9	144553	47	0	0
T10	187791	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	219	0	0
T9	4410	1	0	0
T10	5647	0	0	0
T11	20247	13	0	0
T12	331	0	0	0
T13	729	0	0	0
T14	464	0	0	0
T22	327	0	0	0
T31	1593	0	0	0
T37	0	1	0	0
T38	0	6	0	0
T41	1313	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	1080	0	0	0
T73	0	6	0	0
T86	0	2	0	0
T117	0	1	0	0
T118	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	8832	0	0
T1	396	1	0	0
T2	6515	27	0	0
T3	189	1	0	0
T4	602	2	0	0
T5	414	2	0	0
T6	5672	27	0	0
T7	1090	1	0	0
T8	314	1	0	0
T9	4410	17	0	0
T10	5647	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	21426	0	0
T1	3183	8	0	0
T2	52001	102	0	0
T3	1522	1	0	0
T4	4831	2	0	0
T5	3329	2	0	0
T6	45242	102	0	0
T7	8735	1	0	0
T8	2520	8	0	0
T9	34696	47	0	0
T10	45066	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	21426	0	0
T1	3183	8	0	0
T2	52001	102	0	0
T3	1522	1	0	0
T4	4831	2	0	0
T5	3329	2	0	0
T6	45242	102	0	0
T7	8735	1	0	0
T8	2520	8	0	0
T9	34696	47	0	0
T10	45066	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	21426	0	0
T1	2530	8	0	0
T2	48897	102	0	0
T3	1455	1	0	0
T4	4693	2	0	0
T5	3167	2	0	0
T6	41969	102	0	0
T7	8716	1	0	0
T8	1913	8	0	0
T9	31122	47	0	0
T10	41909	102	0	0