Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_sys.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_ctrl_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_io.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_sys.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	16632	16632	0	0
OutputsKnown_A	368545186	207264716	0	0
gen_no_flops.OutputDelay_A	368545186	207264716	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16632	16632	0	0
T1	33	33	0	0
T2	33	33	0	0
T3	33	33	0	0
T4	33	33	0	0
T5	33	33	0	0
T6	33	33	0	0
T7	33	33	0	0
T8	33	33	0	0
T9	33	33	0	0
T10	33	33	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368545186	207264716	0	0
T1	84143	59874	0	0
T2	1616705	1036713	0	0
T3	48082	28201	0	0
T4	155007	26106	0	0
T5	104673	26117	0	0
T6	1388250	814945	0	0
T7	287647	266098	0	0
T8	63736	41269	0	0
T9	1030600	758429	0	0
T10	1386154	810857	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368545186	207264716	0	0
T1	84143	59874	0	0
T2	1616705	1036713	0	0
T3	48082	28201	0	0
T4	155007	26106	0	0
T5	104673	26117	0	0
T6	1388250	814945	0	0
T7	287647	266098	0	0
T8	63736	41269	0	0
T9	1030600	758429	0	0
T10	1386154	810857	0	0

Line Coverage for Instance : tb.dut.u_ctrl_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_ctrl_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	12538562	7319916	0	0
gen_no_flops.OutputDelay_A	12538562	7319916	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	7319916	0	0
T1	3183	2530	0	0
T2	52001	34633	0	0
T3	1522	873	0	0
T4	4831	890	0	0
T5	3329	1029	0	0
T6	45242	27905	0	0
T7	8735	8082	0	0
T8	2520	1877	0	0
T9	34696	25373	0	0
T10	45066	27689	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	7319916	0	0
T1	3183	2530	0	0
T2	52001	34633	0	0
T3	1522	873	0	0
T4	4831	890	0	0
T5	3329	1029	0	0
T6	45242	27905	0	0
T7	8735	8082	0	0
T8	2520	1877	0	0
T9	34696	25373	0	0
T10	45066	27689	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	504	504	0	0
OutputsKnown_A	11125207	6248275	0	0
gen_no_flops.OutputDelay_A	11125207	6248275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504	504	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11125207	6248275	0	0
T1	2530	1792	0	0
T2	48897	31315	0	0
T3	1455	854	0	0
T4	4693	788	0	0
T5	3167	784	0	0
T6	41969	24595	0	0
T7	8716	8063	0	0
T8	1913	1231	0	0
T9	31122	22908	0	0
T10	41909	24474	0	0