Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T22
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T31
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T31
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T31
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T31
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T31
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12538562	13437	0	0
gen_assertions[0].RstEnOn_A	12538562	1030	0	0
gen_assertions[0].RstNOff_A	12538562	13437	0	0
gen_assertions[0].RstNOn_A	12538562	1030	0	0
gen_assertions[1].RstEnOff_A	50154887	12284	0	0
gen_assertions[1].RstEnOn_A	50154887	994	0	0
gen_assertions[1].RstNOff_A	50154887	12284	0	0
gen_assertions[1].RstNOn_A	50154887	994	0	0
gen_assertions[2].RstEnOff_A	25078022	12325	0	0
gen_assertions[2].RstEnOn_A	25078022	972	0	0
gen_assertions[2].RstNOff_A	25078022	12325	0	0
gen_assertions[2].RstNOn_A	25078022	972	0	0
gen_assertions[3].RstEnOff_A	25078098	12358	0	0
gen_assertions[3].RstEnOn_A	25078098	1002	0	0
gen_assertions[3].RstNOff_A	25078098	12358	0	0
gen_assertions[3].RstNOn_A	25078098	1002	0	0
gen_assertions[4].RstEnOff_A	1583728	21219	0	0
gen_assertions[4].RstEnOn_A	1583728	1090	0	0
gen_assertions[4].RstNOff_A	1583728	21219	0	0
gen_assertions[4].RstNOn_A	1583728	1090	0	0
gen_assertions[5].RstEnOff_A	12538562	13673	0	0
gen_assertions[5].RstEnOn_A	12538562	1114	0	0
gen_assertions[5].RstNOff_A	12538562	13673	0	0
gen_assertions[5].RstNOn_A	12538562	1114	0	0
gen_assertions[6].RstEnOff_A	12538562	13741	0	0
gen_assertions[6].RstEnOn_A	12538562	1177	0	0
gen_assertions[6].RstNOff_A	12538562	13741	0	0
gen_assertions[6].RstNOn_A	12538562	1177	0	0
gen_assertions[7].RstEnOff_A	12538562	13798	0	0
gen_assertions[7].RstEnOn_A	12538562	1239	0	0
gen_assertions[7].RstNOff_A	12538562	13798	0	0
gen_assertions[7].RstNOn_A	12538562	1239	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13437	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	0	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	264	0	0
T12	0	4	0	0
T22	0	4	0	0
T31	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1030	0	0
T1	3183	1	0	0
T2	52001	0	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	0	0	0
T7	8735	0	0	0
T8	2520	4	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	0	15	0	0
T31	0	5	0	0
T38	0	12	0	0
T41	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T68	0	7	0	0
T70	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13437	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	0	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	264	0	0
T12	0	4	0	0
T22	0	4	0	0
T31	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1030	0	0
T1	3183	1	0	0
T2	52001	0	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	0	0	0
T7	8735	0	0	0
T8	2520	4	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	0	15	0	0
T31	0	5	0	0
T38	0	12	0	0
T41	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T68	0	7	0	0
T70	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50154887	12284	0	0
T1	12737	7	0	0
T2	207990	68	0	0
T3	6092	0	0	0
T4	19327	0	0	0
T5	13320	0	0	0
T6	181043	68	0	0
T7	34943	2	0	0
T8	10089	6	0	0
T9	138767	27	0	0
T10	180275	64	0	0
T11	0	233	0	0
T12	0	4	0	0
T22	0	1	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50154887	994	0	0
T7	34943	2	0	0
T8	10089	4	0	0
T9	138767	0	0	0
T10	180275	0	0	0
T11	633216	14	0	0
T12	10654	0	0	0
T13	23308	0	0	0
T22	10503	0	0	0
T31	51038	8	0	0
T38	0	11	0	0
T41	42073	2	0	0
T68	0	8	0	0
T70	0	3	0	0
T71	0	20	0	0
T72	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50154887	12284	0	0
T1	12737	7	0	0
T2	207990	68	0	0
T3	6092	0	0	0
T4	19327	0	0	0
T5	13320	0	0	0
T6	181043	68	0	0
T7	34943	2	0	0
T8	10089	6	0	0
T9	138767	27	0	0
T10	180275	64	0	0
T11	0	233	0	0
T12	0	4	0	0
T22	0	1	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50154887	994	0	0
T7	34943	2	0	0
T8	10089	4	0	0
T9	138767	0	0	0
T10	180275	0	0	0
T11	633216	14	0	0
T12	10654	0	0	0
T13	23308	0	0	0
T22	10503	0	0	0
T31	51038	8	0	0
T38	0	11	0	0
T41	42073	2	0	0
T68	0	8	0	0
T70	0	3	0	0
T71	0	20	0	0
T72	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078022	12325	0	0
T1	6369	7	0	0
T2	103998	68	0	0
T3	3046	0	0	0
T4	9664	0	0	0
T5	6659	0	0	0
T6	90502	68	0	0
T7	17472	3	0	0
T8	5043	6	0	0
T9	69384	27	0	0
T10	90138	64	0	0
T11	0	235	0	0
T12	0	4	0	0
T22	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078022	972	0	0
T7	17472	3	0	0
T8	5043	0	0	0
T9	69384	0	0	0
T10	90138	0	0	0
T11	316654	15	0	0
T12	5324	0	0	0
T13	11643	0	0	0
T22	5248	1	0	0
T31	25520	9	0	0
T38	0	10	0	0
T41	21036	5	0	0
T68	0	9	0	0
T70	0	1	0	0
T71	0	23	0	0
T72	0	10	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078022	12325	0	0
T1	6369	7	0	0
T2	103998	68	0	0
T3	3046	0	0	0
T4	9664	0	0	0
T5	6659	0	0	0
T6	90502	68	0	0
T7	17472	3	0	0
T8	5043	6	0	0
T9	69384	27	0	0
T10	90138	64	0	0
T11	0	235	0	0
T12	0	4	0	0
T22	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078022	972	0	0
T7	17472	3	0	0
T8	5043	0	0	0
T9	69384	0	0	0
T10	90138	0	0	0
T11	316654	15	0	0
T12	5324	0	0	0
T13	11643	0	0	0
T22	5248	1	0	0
T31	25520	9	0	0
T38	0	10	0	0
T41	21036	5	0	0
T68	0	9	0	0
T70	0	1	0	0
T71	0	23	0	0
T72	0	10	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078098	12358	0	0
T1	6368	7	0	0
T2	104008	68	0	0
T3	3045	0	0	0
T4	9664	0	0	0
T5	6660	0	0	0
T6	90537	68	0	0
T7	17472	3	0	0
T8	5043	6	0	0
T9	69386	27	0	0
T10	90134	64	0	0
T11	0	235	0	0
T12	0	4	0	0
T22	0	1	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078098	1002	0	0
T7	17472	3	0	0
T8	5043	0	0	0
T9	69386	0	0	0
T10	90134	0	0	0
T11	316623	15	0	0
T12	5324	0	0	0
T13	11650	0	0	0
T22	5249	0	0	0
T31	25519	9	0	0
T38	0	7	0	0
T41	21036	5	0	0
T68	0	10	0	0
T71	0	18	0	0
T72	0	9	0	0
T73	0	10	0	0
T74	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078098	12358	0	0
T1	6368	7	0	0
T2	104008	68	0	0
T3	3045	0	0	0
T4	9664	0	0	0
T5	6660	0	0	0
T6	90537	68	0	0
T7	17472	3	0	0
T8	5043	6	0	0
T9	69386	27	0	0
T10	90134	64	0	0
T11	0	235	0	0
T12	0	4	0	0
T22	0	1	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25078098	1002	0	0
T7	17472	3	0	0
T8	5043	0	0	0
T9	69386	0	0	0
T10	90134	0	0	0
T11	316623	15	0	0
T12	5324	0	0	0
T13	11650	0	0	0
T22	5249	0	0	0
T31	25519	9	0	0
T38	0	7	0	0
T41	21036	5	0	0
T68	0	10	0	0
T71	0	18	0	0
T72	0	9	0	0
T73	0	10	0	0
T74	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	21219	0	0
T1	396	8	0	0
T2	6515	95	0	0
T3	189	1	0	0
T4	602	2	0	0
T5	414	2	0	0
T6	5672	88	0	0
T7	1090	6	0	0
T8	314	7	0	0
T9	4410	46	0	0
T10	5647	92	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	1090	0	0
T7	1090	5	0	0
T8	314	0	0	0
T9	4410	0	0	0
T10	5647	0	0	0
T11	20247	15	0	0
T12	331	0	0	0
T13	729	0	0	0
T22	327	0	0	0
T31	1593	11	0	0
T38	0	12	0	0
T41	1313	7	0	0
T64	0	1	0	0
T68	0	11	0	0
T71	0	17	0	0
T72	0	10	0	0
T75	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	21219	0	0
T1	396	8	0	0
T2	6515	95	0	0
T3	189	1	0	0
T4	602	2	0	0
T5	414	2	0	0
T6	5672	88	0	0
T7	1090	6	0	0
T8	314	7	0	0
T9	4410	46	0	0
T10	5647	92	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583728	1090	0	0
T7	1090	5	0	0
T8	314	0	0	0
T9	4410	0	0	0
T10	5647	0	0	0
T11	20247	15	0	0
T12	331	0	0	0
T13	729	0	0	0
T22	327	0	0	0
T31	1593	11	0	0
T38	0	12	0	0
T41	1313	7	0	0
T64	0	1	0	0
T68	0	11	0	0
T71	0	17	0	0
T72	0	10	0	0
T75	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13673	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	5	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	265	0	0
T12	0	4	0	0
T22	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1114	0	0
T7	8735	5	0	0
T8	2520	0	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	158301	14	0	0
T12	2661	0	0	0
T13	5824	0	0	0
T22	2623	0	0	0
T31	12758	12	0	0
T38	0	8	0	0
T41	10517	8	0	0
T68	0	11	0	0
T71	0	19	0	0
T72	0	12	0	0
T73	0	11	0	0
T76	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13673	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	5	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	265	0	0
T12	0	4	0	0
T22	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1114	0	0
T7	8735	5	0	0
T8	2520	0	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	158301	14	0	0
T12	2661	0	0	0
T13	5824	0	0	0
T22	2623	0	0	0
T31	12758	12	0	0
T38	0	8	0	0
T41	10517	8	0	0
T68	0	11	0	0
T71	0	19	0	0
T72	0	12	0	0
T73	0	11	0	0
T76	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13741	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	7	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	264	0	0
T12	0	4	0	0
T22	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1177	0	0
T7	8735	7	0	0
T8	2520	0	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	158301	14	0	0
T12	2661	0	0	0
T13	5824	0	0	0
T22	2623	0	0	0
T31	12758	14	0	0
T38	0	10	0	0
T41	10517	8	0	0
T68	0	14	0	0
T71	0	17	0	0
T72	0	15	0	0
T73	0	10	0	0
T76	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13741	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	7	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	264	0	0
T12	0	4	0	0
T22	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1177	0	0
T7	8735	7	0	0
T8	2520	0	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	158301	14	0	0
T12	2661	0	0	0
T13	5824	0	0	0
T22	2623	0	0	0
T31	12758	14	0	0
T38	0	10	0	0
T41	10517	8	0	0
T68	0	14	0	0
T71	0	17	0	0
T72	0	15	0	0
T73	0	10	0	0
T76	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13798	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	8	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	264	0	0
T12	0	4	0	0
T22	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1239	0	0
T7	8735	8	0	0
T8	2520	0	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	158301	14	0	0
T12	2661	0	0	0
T13	5824	0	0	0
T22	2623	0	0	0
T31	12758	15	0	0
T38	0	12	0	0
T41	10517	10	0	0
T65	0	1	0	0
T68	0	15	0	0
T71	0	17	0	0
T72	0	16	0	0
T76	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	13798	0	0
T1	3183	7	0	0
T2	52001	75	0	0
T3	1522	0	0	0
T4	4831	0	0	0
T5	3329	0	0	0
T6	45242	75	0	0
T7	8735	8	0	0
T8	2520	7	0	0
T9	34696	30	0	0
T10	45066	75	0	0
T11	0	264	0	0
T12	0	4	0	0
T22	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12538562	1239	0	0
T7	8735	8	0	0
T8	2520	0	0	0
T9	34696	0	0	0
T10	45066	0	0	0
T11	158301	14	0	0
T12	2661	0	0	0
T13	5824	0	0	0
T22	2623	0	0	0
T31	12758	15	0	0
T38	0	12	0	0
T41	10517	10	0	0
T65	0	1	0	0
T68	0	15	0	0
T71	0	17	0	0
T72	0	16	0	0
T76	0	1	0	0