Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11943447	9438	0	0
alert_regwen_rd_A	11943447	5098	0	0
cpu_regwen_rd_A	11943447	5121	0	0
sw_rst_ctrl_n_0_rd_A	11943447	9475	0	0
sw_rst_ctrl_n_1_rd_A	11943447	9388	0	0
sw_rst_ctrl_n_2_rd_A	11943447	9232	0	0
sw_rst_ctrl_n_3_rd_A	11943447	9465	0	0
sw_rst_ctrl_n_4_rd_A	11943447	9157	0	0
sw_rst_ctrl_n_5_rd_A	11943447	9474	0	0
sw_rst_ctrl_n_6_rd_A	11943447	9463	0	0
sw_rst_ctrl_n_7_rd_A	11943447	9533	0	0
sw_rst_regwen_0_rd_A	11943447	5792	0	0
sw_rst_regwen_1_rd_A	11943447	5739	0	0
sw_rst_regwen_2_rd_A	11943447	5713	0	0
sw_rst_regwen_3_rd_A	11943447	5743	0	0
sw_rst_regwen_4_rd_A	11943447	5568	0	0
sw_rst_regwen_5_rd_A	11943447	5695	0	0
sw_rst_regwen_6_rd_A	11943447	5863	0	0
sw_rst_regwen_7_rd_A	11943447	5751	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9438	0	0
T45	5163	256	0	0
T46	11135	755	0	0
T47	2716	359	0	0
T53	4062	15	0	0
T54	21836	3	0	0
T80	6891	248	0	0
T81	4337	18	0	0
T82	4721	545	0	0
T83	11246	644	0	0
T111	20609	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5098	0	0
T9	31122	62	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T14	3609	0	0	0
T22	2482	0	0	0
T31	12741	0	0	0
T41	10427	0	0	0
T66	0	74	0	0
T68	8589	0	0	0
T73	0	197	0	0
T87	0	87	0	0
T90	0	54	0	0
T92	0	114	0	0
T112	0	59	0	0
T113	0	76	0	0
T114	0	157	0	0
T115	0	371	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5121	0	0
T9	31122	27	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T14	3609	0	0	0
T22	2482	0	0	0
T31	12741	0	0	0
T41	10427	0	0	0
T66	0	122	0	0
T68	8589	0	0	0
T73	0	158	0	0
T87	0	107	0	0
T90	0	33	0	0
T92	0	84	0	0
T112	0	58	0	0
T113	0	83	0	0
T114	0	156	0	0
T115	0	345	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9475	0	0
T1	2530	7	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	122	0	0
T8	1913	0	0	0
T9	31122	35	0	0
T10	41909	0	0	0
T31	0	242	0	0
T41	0	145	0	0
T64	0	15	0	0
T66	0	46	0	0
T76	0	16	0	0
T87	0	88	0	0
T116	0	14	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9388	0	0
T1	2530	5	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	114	0	0
T8	1913	0	0	0
T9	31122	33	0	0
T10	41909	0	0	0
T31	0	186	0	0
T41	0	150	0	0
T64	0	3	0	0
T66	0	70	0	0
T76	0	24	0	0
T87	0	108	0	0
T116	0	16	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9232	0	0
T1	2530	19	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	116	0	0
T8	1913	0	0	0
T9	31122	9	0	0
T10	41909	0	0	0
T31	0	216	0	0
T41	0	145	0	0
T64	0	14	0	0
T66	0	80	0	0
T76	0	14	0	0
T87	0	84	0	0
T116	0	4	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9465	0	0
T1	2530	9	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	144	0	0
T8	1913	0	0	0
T9	31122	42	0	0
T10	41909	0	0	0
T31	0	204	0	0
T41	0	158	0	0
T64	0	10	0	0
T66	0	90	0	0
T76	0	14	0	0
T87	0	82	0	0
T116	0	26	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9157	0	0
T1	2530	21	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	98	0	0
T8	1913	0	0	0
T9	31122	39	0	0
T10	41909	0	0	0
T31	0	231	0	0
T41	0	158	0	0
T64	0	13	0	0
T66	0	74	0	0
T76	0	9	0	0
T87	0	74	0	0
T116	0	7	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9474	0	0
T1	2530	29	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	114	0	0
T8	1913	0	0	0
T9	31122	16	0	0
T10	41909	0	0	0
T31	0	169	0	0
T41	0	167	0	0
T64	0	9	0	0
T66	0	62	0	0
T76	0	14	0	0
T87	0	128	0	0
T116	0	6	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9463	0	0
T1	2530	11	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	112	0	0
T8	1913	0	0	0
T9	31122	21	0	0
T10	41909	0	0	0
T31	0	201	0	0
T41	0	159	0	0
T64	0	13	0	0
T66	0	81	0	0
T76	0	6	0	0
T87	0	109	0	0
T116	0	13	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	9533	0	0
T1	2530	10	0	0
T2	48897	0	0	0
T3	1455	0	0	0
T4	4693	0	0	0
T5	3167	0	0	0
T6	41969	0	0	0
T7	8716	134	0	0
T8	1913	0	0	0
T9	31122	64	0	0
T10	41909	0	0	0
T31	0	203	0	0
T41	0	158	0	0
T64	0	1	0	0
T66	0	95	0	0
T76	0	25	0	0
T87	0	124	0	0
T116	0	16	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5792	0	0
T7	8716	15	0	0
T8	1913	0	0	0
T9	31122	18	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	31	0	0
T41	10427	29	0	0
T64	0	1	0	0
T66	0	67	0	0
T73	0	185	0	0
T76	0	8	0	0
T87	0	94	0	0
T90	0	33	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5739	0	0
T7	8716	40	0	0
T8	1913	0	0	0
T9	31122	34	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	32	0	0
T41	10427	36	0	0
T64	0	3	0	0
T66	0	83	0	0
T73	0	126	0	0
T76	0	3	0	0
T87	0	94	0	0
T90	0	27	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5713	0	0
T7	8716	35	0	0
T8	1913	0	0	0
T9	31122	35	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	31	0	0
T41	10427	43	0	0
T64	0	8	0	0
T66	0	88	0	0
T73	0	172	0	0
T76	0	10	0	0
T87	0	83	0	0
T90	0	22	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5743	0	0
T7	8716	28	0	0
T8	1913	0	0	0
T9	31122	44	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	28	0	0
T41	10427	35	0	0
T64	0	2	0	0
T66	0	75	0	0
T73	0	147	0	0
T76	0	4	0	0
T87	0	104	0	0
T90	0	46	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5568	0	0
T7	8716	28	0	0
T8	1913	0	0	0
T9	31122	11	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	28	0	0
T41	10427	30	0	0
T64	0	8	0	0
T66	0	73	0	0
T73	0	185	0	0
T76	0	3	0	0
T87	0	70	0	0
T90	0	42	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5695	0	0
T7	8716	32	0	0
T8	1913	0	0	0
T9	31122	48	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	37	0	0
T41	10427	34	0	0
T64	0	5	0	0
T66	0	83	0	0
T73	0	208	0	0
T76	0	9	0	0
T87	0	70	0	0
T90	0	30	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5863	0	0
T7	8716	41	0	0
T8	1913	0	0	0
T9	31122	25	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	42	0	0
T41	10427	32	0	0
T64	0	7	0	0
T66	0	79	0	0
T73	0	187	0	0
T76	0	9	0	0
T87	0	109	0	0
T90	0	41	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11943447	5751	0	0
T7	8716	35	0	0
T8	1913	0	0	0
T9	31122	21	0	0
T10	41909	0	0	0
T11	124053	0	0	0
T12	2420	0	0	0
T13	5087	0	0	0
T22	2482	0	0	0
T31	12741	17	0	0
T41	10427	18	0	0
T64	0	8	0	0
T66	0	71	0	0
T73	0	163	0	0
T76	0	9	0	0
T87	0	58	0	0
T90	0	39	0	0