Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11043460	12851	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11043460	118705	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11043460	6242298	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11043460	189611	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11043460	12851	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11043460	118705	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11043460	6242298	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11043460	189611	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	12851	0	0
T1	2730	4	0	0
T2	3005	0	0	0
T3	3427	4	0	0
T4	1538	0	0	0
T5	1794	4	0	0
T6	2637	6	0	0
T7	2819	0	0	0
T8	2679	4	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0
T23	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	118705	0	0
T1	2730	38	0	0
T2	3005	0	0	0
T3	3427	38	0	0
T4	1538	0	0	0
T5	1794	36	0	0
T6	2637	54	0	0
T7	2819	0	0	0
T8	2679	38	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	0	240	0	0
T12	0	38	0	0
T13	0	307	0	0
T22	0	27	0	0
T23	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6242298	0	0
T1	2730	1744	0	0
T2	3005	697	0	0
T3	3427	2425	0	0
T4	1538	901	0	0
T5	1794	1115	0	0
T6	2637	1972	0	0
T7	2819	670	0	0
T8	2679	1717	0	0
T9	5310	597	0	0
T10	6499	5860	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	189611	0	0
T1	2730	49	0	0
T2	3005	0	0	0
T3	3427	61	0	0
T4	1538	0	0	0
T5	1794	43	0	0
T6	2637	92	0	0
T7	2819	0	0	0
T8	2679	64	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	0	404	0	0
T12	0	63	0	0
T13	0	516	0	0
T22	0	36	0	0
T23	0	48	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	12851	0	0
T1	2730	4	0	0
T2	3005	0	0	0
T3	3427	4	0	0
T4	1538	0	0	0
T5	1794	4	0	0
T6	2637	6	0	0
T7	2819	0	0	0
T8	2679	4	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0
T23	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	118705	0	0
T1	2730	38	0	0
T2	3005	0	0	0
T3	3427	38	0	0
T4	1538	0	0	0
T5	1794	36	0	0
T6	2637	54	0	0
T7	2819	0	0	0
T8	2679	38	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	0	240	0	0
T12	0	38	0	0
T13	0	307	0	0
T22	0	27	0	0
T23	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6242298	0	0
T1	2730	1744	0	0
T2	3005	697	0	0
T3	3427	2425	0	0
T4	1538	901	0	0
T5	1794	1115	0	0
T6	2637	1972	0	0
T7	2819	670	0	0
T8	2679	1717	0	0
T9	5310	597	0	0
T10	6499	5860	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	189611	0	0
T1	2730	49	0	0
T2	3005	0	0	0
T3	3427	61	0	0
T4	1538	0	0	0
T5	1794	43	0	0
T6	2637	92	0	0
T7	2819	0	0	0
T8	2679	64	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	0	404	0	0
T12	0	63	0	0
T13	0	516	0	0
T22	0	36	0	0
T23	0	48	0	0