Unified Coverage Report :: Module :: rstmgr

Module : rstmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	99.55	100.00	98.21	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	99.40	99.31	99.87		99.83	99.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00				100.00	100.00
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon	96.65	95.83	97.44			93.33	100.00
gen_rst_por_aon[0].u_por_scanmode_sync	100.00	100.00					100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux	100.00	100.00	100.00				100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync	100.00	100.00				100.00
gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00				100.00	100.00
gen_rst_por_aon[1].u_por_scanmode_sync	100.00	100.00					100.00
pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00
rstmgr_attrs_sva_if	100.00						100.00
rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00
rstmgr_csr_assert	100.00						100.00
rstmgr_rst_en_track_sva_if	92.86						92.86
rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_alert_info	100.00	100.00				100.00	100.00
u_cpu_info	100.00	100.00				100.00	100.00
u_ctrl_scanmode_sync	100.00	100.00					100.00
u_d0_i2c0	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_i2c1	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_i2c2	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_lc	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_lc_io	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_lc_io_div2	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_lc_io_div4	100.00	100.00	100.00			100.00	100.00
u_d0_lc_io_div4_shadowed	100.00	100.00	100.00			100.00	100.00
u_d0_lc_shadowed	96.47	100.00	100.00	82.35		100.00	100.00
u_d0_lc_usb	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_spi_device	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_spi_host0	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_spi_host1	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_sys	100.00	100.00	100.00	100.00		100.00	100.00
u_d0_usb	99.29	100.00	96.43	100.00		100.00	100.00
u_d0_usb_aon	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_aon	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_io	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_io_div2	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_io_div4	100.00	100.00	100.00			100.00	100.00
u_daon_lc_io_div4_shadowed	100.00	100.00	100.00			100.00	100.00
u_daon_lc_shadowed	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_lc_usb	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_io	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_io_div2	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_io_div4	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_por_usb	100.00	100.00	100.00	100.00		100.00	100.00
u_daon_sys_io_div4	100.00	100.00	100.00	100.00		100.00	100.00
u_lc_src	100.00	100.00	100.00			100.00	100.00
u_por_clk_buf	100.00	100.00
u_por_rst_buf	100.00	100.00
u_reg	99.65	98.40	99.85	100.00		100.00	100.00
u_sys_src	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
CONT_ASSIGN	1187	1	1	100.00
CONT_ASSIGN	1189	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1197	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1212	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00

141                       end
142        1/1            assign resets_o.rst_por_aon_n = rst_por_aon_n;
           Tests:       T1 T2 T3 
143                     
144                       logic clk_por;
145                       logic rst_por_n;
146                       prim_clock_buf #(
147                         .NoFpgaBuf(1'b1)
148                       ) u_por_clk_buf (
149                         .clk_i(clk_por_i),
150                         .clk_o(clk_por)
151                       );
152                     
153                       prim_clock_buf #(
154                         .NoFpgaBuf(1'b1)
155                       ) u_por_rst_buf (
156                         .clk_i(rst_por_ni),
157                         .clk_o(rst_por_n)
158                       );
159                     
160                       ////////////////////////////////////////////////////
161                       // Register Interface                             //
162                       ////////////////////////////////////////////////////
163                     
164                       rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw;
165                       rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg;
166                     
167                       logic reg_intg_err;
168                       // SEC_CM: BUS.INTEGRITY
169                       // SEC_CM: SW_RST.CONFIG.REGWEN, DUMP_CTRL.CONFIG.REGWEN
170                       rstmgr_reg_top u_reg (
171                         .clk_i,
172                         .rst_ni,
173                         .clk_por_i  (clk_por),
174                         .rst_por_ni (rst_por_n),
175                         .tl_i,
176                         .tl_o,
177                         .reg2hw,
178                         .hw2reg,
179                         .intg_err_o(reg_intg_err)
180                       );
181                     
182                     
183                       ////////////////////////////////////////////////////
184                       // Errors                                         //
185                       ////////////////////////////////////////////////////
186                     
187                       // consistency check errors
188                       logic [20:0][PowerDomains-1:0] cnsty_chk_errs;
189                       logic [20:0][PowerDomains-1:0] shadow_cnsty_chk_errs;
190                     
191                       // consistency sparse fsm errors
192                       logic [20:0][PowerDomains-1:0] fsm_errs;
193                       logic [20:0][PowerDomains-1:0] shadow_fsm_errs;
194                     
195                       assign hw2reg.err_code.reg_intg_err.d  = 1'b1;
196        1/1            assign hw2reg.err_code.reg_intg_err.de = reg_intg_err;
           Tests:       T1 T3 T4 
197                       assign hw2reg.err_code.reset_consistency_err.d  = 1'b1;
198        1/1            assign hw2reg.err_code.reset_consistency_err.de = |cnsty_chk_errs ||
           Tests:       T9 T24 T73 
199                                                                         |shadow_cnsty_chk_errs;
200                       assign hw2reg.err_code.fsm_err.d  = 1'b1;
201        1/1            assign hw2reg.err_code.fsm_err.de = |fsm_errs || |shadow_fsm_errs;
           Tests:       T54 T74 T75 
202                       ////////////////////////////////////////////////////
203                       // Alerts                                         //
204                       ////////////////////////////////////////////////////
205                       logic [NumAlerts-1:0] alert_test, alerts;
206                     
207                       // All of these are fatal alerts
208        1/1            assign alerts[0] = reg2hw.err_code.reg_intg_err.q |
           Tests:       T54 T74 T75 
209                                          (|reg2hw.err_code.fsm_err.q);
210                     
211        1/1            assign alerts[1] = reg2hw.err_code.reset_consistency_err.q;
           Tests:       T9 T24 T73 
212                     
213        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
214                         reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe,
215                         reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe
216                       };
217                     
218                       for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
219                         prim_alert_sender #(
220                           .AsyncOn(AlertAsyncOn[i]),
221                           .IsFatal(1'b1)
222                         ) u_prim_alert_sender (
223                           .clk_i,
224                           .rst_ni,
225                           .alert_test_i  ( alert_test[i] ),
226                           .alert_req_i   ( alerts[i]     ),
227                           .alert_ack_o   (               ),
228                           .alert_state_o (               ),
229                           .alert_rx_i    ( alert_rx_i[i] ),
230                           .alert_tx_o    ( alert_tx_o[i] )
231                         );
232                       end
233                     
234                       ////////////////////////////////////////////////////
235                       // Source resets in the system                    //
236                       // These are hardcoded and not directly used.     //
237                       // Instead they act as async reset roots.         //
238                       ////////////////////////////////////////////////////
239                     
240                       // The two source reset modules are chained together.  The output of one is fed into the
241                       // the second.  This ensures that if upstream resets for any reason, the associated downstream
242                       // reset will also reset.
243                     
244                       logic [PowerDomains-1:0] rst_lc_src_n;
245                       logic [PowerDomains-1:0] rst_sys_src_n;
246                     
247                       // Declared as size 1 packed array to avoid FPV warning.
248                       prim_mubi_pkg::mubi4_t [0:0] rst_ctrl_scanmode;
249                       prim_mubi4_sync #(
250                         .NumCopies(1),
251                         .AsyncOn(0)
252                       ) u_ctrl_scanmode_sync (
253                         .clk_i (clk_por),
254                         .rst_ni (rst_por_n),
255                         .mubi_i(scanmode_i),
256                         .mubi_o(rst_ctrl_scanmode)
257                       );
258                     
259                       // lc reset sources
260                       rstmgr_ctrl u_lc_src (
261                         .clk_i (clk_por),
262                         .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])),
263                         .scan_rst_ni,
264                         .rst_req_i(pwr_i.rst_lc_req),
265                         .rst_parent_ni(rst_por_aon_n),
266                         .rst_no(rst_lc_src_n)
267                       );
268                     
269                       // sys reset sources
270                       rstmgr_ctrl u_sys_src (
271                         .clk_i (clk_por),
272                         .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])),
273                         .scan_rst_ni,
274                         .rst_req_i(pwr_i.rst_sys_req),
275                         .rst_parent_ni(rst_por_aon_n),
276                         .rst_no(rst_sys_src_n)
277                       );
278                     
279        1/1            assign pwr_o.rst_lc_src_n = rst_lc_src_n;
           Tests:       T1 T2 T3 
280        1/1            assign pwr_o.rst_sys_src_n = rst_sys_src_n;
           Tests:       T1 T2 T3 
281                     
282                     
283                       ////////////////////////////////////////////////////
284                       // leaf reset in the system                       //
285                       // These should all be generated                  //
286                       ////////////////////////////////////////////////////
287                       // To simplify generation, each reset generates all associated power domain outputs.
288                       // If a reset does not support a particular power domain, that reset is always hard-wired to 0.
289                     
290                       // Generating resets for por
291                       // Power Domains: ['Aon']
292                       // Shadowed: False
293                       rstmgr_leaf_rst #(
294                         .SecCheck(SecCheck),
295                         .SecMaxSyncDelay(SecMaxSyncDelay),
296                         .SwRstReq(1'b0)
297                       ) u_daon_por (
298                         .clk_i,
299                         .rst_ni,
300                         .leaf_clk_i(clk_main_i),
301                         .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
302                         .sw_rst_req_ni(1'b1),
303                         .scan_rst_ni,
304                         .scanmode_i,
305                         .rst_en_o(rst_en_o.por[DomainAonSel]),
306                         .leaf_rst_o(resets_o.rst_por_n[DomainAonSel]),
307                         .err_o(cnsty_chk_errs[0][DomainAonSel]),
308                         .fsm_err_o(fsm_errs[0][DomainAonSel])
309                       );
310                     
311                       if (SecCheck) begin : gen_daon_por_assert
312                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
313                         DAonPorFsmCheck_A,
314                         u_daon_por.gen_rst_chk.u_rst_chk.u_state_regs,
315                         alert_tx_o[0])
316                       end
317                       assign resets_o.rst_por_n[Domain0Sel] = '0;
318                       assign cnsty_chk_errs[0][Domain0Sel] = '0;
319                       assign fsm_errs[0][Domain0Sel] = '0;
320                       assign rst_en_o.por[Domain0Sel] = MuBi4True;
321                       assign shadow_cnsty_chk_errs[0] = '0;
322                       assign shadow_fsm_errs[0] = '0;
323                     
324                       // Generating resets for por_io
325                       // Power Domains: ['Aon']
326                       // Shadowed: False
327                       rstmgr_leaf_rst #(
328                         .SecCheck(SecCheck),
329                         .SecMaxSyncDelay(SecMaxSyncDelay),
330                         .SwRstReq(1'b0)
331                       ) u_daon_por_io (
332                         .clk_i,
333                         .rst_ni,
334                         .leaf_clk_i(clk_io_i),
335                         .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
336                         .sw_rst_req_ni(1'b1),
337                         .scan_rst_ni,
338                         .scanmode_i,
339                         .rst_en_o(rst_en_o.por_io[DomainAonSel]),
340                         .leaf_rst_o(resets_o.rst_por_io_n[DomainAonSel]),
341                         .err_o(cnsty_chk_errs[1][DomainAonSel]),
342                         .fsm_err_o(fsm_errs[1][DomainAonSel])
343                       );
344                     
345                       if (SecCheck) begin : gen_daon_por_io_assert
346                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
347                         DAonPorIoFsmCheck_A,
348                         u_daon_por_io.gen_rst_chk.u_rst_chk.u_state_regs,
349                         alert_tx_o[0])
350                       end
351                       assign resets_o.rst_por_io_n[Domain0Sel] = '0;
352                       assign cnsty_chk_errs[1][Domain0Sel] = '0;
353                       assign fsm_errs[1][Domain0Sel] = '0;
354                       assign rst_en_o.por_io[Domain0Sel] = MuBi4True;
355                       assign shadow_cnsty_chk_errs[1] = '0;
356                       assign shadow_fsm_errs[1] = '0;
357                     
358                       // Generating resets for por_io_div2
359                       // Power Domains: ['Aon']
360                       // Shadowed: False
361                       rstmgr_leaf_rst #(
362                         .SecCheck(SecCheck),
363                         .SecMaxSyncDelay(SecMaxSyncDelay),
364                         .SwRstReq(1'b0)
365                       ) u_daon_por_io_div2 (
366                         .clk_i,
367                         .rst_ni,
368                         .leaf_clk_i(clk_io_div2_i),
369                         .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
370                         .sw_rst_req_ni(1'b1),
371                         .scan_rst_ni,
372                         .scanmode_i,
373                         .rst_en_o(rst_en_o.por_io_div2[DomainAonSel]),
374                         .leaf_rst_o(resets_o.rst_por_io_div2_n[DomainAonSel]),
375                         .err_o(cnsty_chk_errs[2][DomainAonSel]),
376                         .fsm_err_o(fsm_errs[2][DomainAonSel])
377                       );
378                     
379                       if (SecCheck) begin : gen_daon_por_io_div2_assert
380                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
381                         DAonPorIoDiv2FsmCheck_A,
382                         u_daon_por_io_div2.gen_rst_chk.u_rst_chk.u_state_regs,
383                         alert_tx_o[0])
384                       end
385                       assign resets_o.rst_por_io_div2_n[Domain0Sel] = '0;
386                       assign cnsty_chk_errs[2][Domain0Sel] = '0;
387                       assign fsm_errs[2][Domain0Sel] = '0;
388                       assign rst_en_o.por_io_div2[Domain0Sel] = MuBi4True;
389                       assign shadow_cnsty_chk_errs[2] = '0;
390                       assign shadow_fsm_errs[2] = '0;
391                     
392                       // Generating resets for por_io_div4
393                       // Power Domains: ['Aon']
394                       // Shadowed: False
395                       rstmgr_leaf_rst #(
396                         .SecCheck(SecCheck),
397                         .SecMaxSyncDelay(SecMaxSyncDelay),
398                         .SwRstReq(1'b0)
399                       ) u_daon_por_io_div4 (
400                         .clk_i,
401                         .rst_ni,
402                         .leaf_clk_i(clk_io_div4_i),
403                         .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
404                         .sw_rst_req_ni(1'b1),
405                         .scan_rst_ni,
406                         .scanmode_i,
407                         .rst_en_o(rst_en_o.por_io_div4[DomainAonSel]),
408                         .leaf_rst_o(resets_o.rst_por_io_div4_n[DomainAonSel]),
409                         .err_o(cnsty_chk_errs[3][DomainAonSel]),
410                         .fsm_err_o(fsm_errs[3][DomainAonSel])
411                       );
412                     
413                       if (SecCheck) begin : gen_daon_por_io_div4_assert
414                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
415                         DAonPorIoDiv4FsmCheck_A,
416                         u_daon_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs,
417                         alert_tx_o[0])
418                       end
419                       assign resets_o.rst_por_io_div4_n[Domain0Sel] = '0;
420                       assign cnsty_chk_errs[3][Domain0Sel] = '0;
421                       assign fsm_errs[3][Domain0Sel] = '0;
422                       assign rst_en_o.por_io_div4[Domain0Sel] = MuBi4True;
423                       assign shadow_cnsty_chk_errs[3] = '0;
424                       assign shadow_fsm_errs[3] = '0;
425                     
426                       // Generating resets for por_usb
427                       // Power Domains: ['Aon']
428                       // Shadowed: False
429                       rstmgr_leaf_rst #(
430                         .SecCheck(SecCheck),
431                         .SecMaxSyncDelay(SecMaxSyncDelay),
432                         .SwRstReq(1'b0)
433                       ) u_daon_por_usb (
434                         .clk_i,
435                         .rst_ni,
436                         .leaf_clk_i(clk_usb_i),
437                         .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
438                         .sw_rst_req_ni(1'b1),
439                         .scan_rst_ni,
440                         .scanmode_i,
441                         .rst_en_o(rst_en_o.por_usb[DomainAonSel]),
442                         .leaf_rst_o(resets_o.rst_por_usb_n[DomainAonSel]),
443                         .err_o(cnsty_chk_errs[4][DomainAonSel]),
444                         .fsm_err_o(fsm_errs[4][DomainAonSel])
445                       );
446                     
447                       if (SecCheck) begin : gen_daon_por_usb_assert
448                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
449                         DAonPorUsbFsmCheck_A,
450                         u_daon_por_usb.gen_rst_chk.u_rst_chk.u_state_regs,
451                         alert_tx_o[0])
452                       end
453                       assign resets_o.rst_por_usb_n[Domain0Sel] = '0;
454                       assign cnsty_chk_errs[4][Domain0Sel] = '0;
455                       assign fsm_errs[4][Domain0Sel] = '0;
456                       assign rst_en_o.por_usb[Domain0Sel] = MuBi4True;
457                       assign shadow_cnsty_chk_errs[4] = '0;
458                       assign shadow_fsm_errs[4] = '0;
459                     
460                       // Generating resets for lc
461                       // Power Domains: ['0', 'Aon']
462                       // Shadowed: True
463                       rstmgr_leaf_rst #(
464                         .SecCheck(SecCheck),
465                         .SecMaxSyncDelay(SecMaxSyncDelay),
466                         .SwRstReq(1'b0)
467                       ) u_daon_lc (
468                         .clk_i,
469                         .rst_ni,
470                         .leaf_clk_i(clk_main_i),
471                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
472                         .sw_rst_req_ni(1'b1),
473                         .scan_rst_ni,
474                         .scanmode_i,
475                         .rst_en_o(rst_en_o.lc[DomainAonSel]),
476                         .leaf_rst_o(resets_o.rst_lc_n[DomainAonSel]),
477                         .err_o(cnsty_chk_errs[5][DomainAonSel]),
478                         .fsm_err_o(fsm_errs[5][DomainAonSel])
479                       );
480                     
481                       if (SecCheck) begin : gen_daon_lc_assert
482                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
483                         DAonLcFsmCheck_A,
484                         u_daon_lc.gen_rst_chk.u_rst_chk.u_state_regs,
485                         alert_tx_o[0])
486                       end
487                       rstmgr_leaf_rst #(
488                         .SecCheck(SecCheck),
489                         .SecMaxSyncDelay(SecMaxSyncDelay),
490                         .SwRstReq(1'b0)
491                       ) u_d0_lc (
492                         .clk_i,
493                         .rst_ni,
494                         .leaf_clk_i(clk_main_i),
495                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
496                         .sw_rst_req_ni(1'b1),
497                         .scan_rst_ni,
498                         .scanmode_i,
499                         .rst_en_o(rst_en_o.lc[Domain0Sel]),
500                         .leaf_rst_o(resets_o.rst_lc_n[Domain0Sel]),
501                         .err_o(cnsty_chk_errs[5][Domain0Sel]),
502                         .fsm_err_o(fsm_errs[5][Domain0Sel])
503                       );
504                     
505                       if (SecCheck) begin : gen_d0_lc_assert
506                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
507                         D0LcFsmCheck_A,
508                         u_d0_lc.gen_rst_chk.u_rst_chk.u_state_regs,
509                         alert_tx_o[0])
510                       end
511                       rstmgr_leaf_rst #(
512                         .SecCheck(SecCheck),
513                         .SecMaxSyncDelay(SecMaxSyncDelay),
514                         .SwRstReq(1'b0)
515                       ) u_daon_lc_shadowed (
516                         .clk_i,
517                         .rst_ni,
518                         .leaf_clk_i(clk_main_i),
519                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
520                         .sw_rst_req_ni(1'b1),
521                         .scan_rst_ni,
522                         .scanmode_i,
523                         .rst_en_o(rst_en_o.lc_shadowed[DomainAonSel]),
524                         .leaf_rst_o(resets_o.rst_lc_shadowed_n[DomainAonSel]),
525                         .err_o(shadow_cnsty_chk_errs[5][DomainAonSel]),
526                         .fsm_err_o(shadow_fsm_errs[5][DomainAonSel])
527                       );
528                     
529                       if (SecCheck) begin : gen_daon_lc_shadowed_assert
530                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
531                         DAonLcShadowedFsmCheck_A,
532                         u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs,
533                         alert_tx_o[0])
534                       end
535                       rstmgr_leaf_rst #(
536                         .SecCheck(SecCheck),
537                         .SecMaxSyncDelay(SecMaxSyncDelay),
538                         .SwRstReq(1'b0)
539                       ) u_d0_lc_shadowed (
540                         .clk_i,
541                         .rst_ni,
542                         .leaf_clk_i(clk_main_i),
543                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
544                         .sw_rst_req_ni(1'b1),
545                         .scan_rst_ni,
546                         .scanmode_i,
547                         .rst_en_o(rst_en_o.lc_shadowed[Domain0Sel]),
548                         .leaf_rst_o(resets_o.rst_lc_shadowed_n[Domain0Sel]),
549                         .err_o(shadow_cnsty_chk_errs[5][Domain0Sel]),
550                         .fsm_err_o(shadow_fsm_errs[5][Domain0Sel])
551                       );
552                     
553                       if (SecCheck) begin : gen_d0_lc_shadowed_assert
554                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
555                         D0LcShadowedFsmCheck_A,
556                         u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs,
557                         alert_tx_o[0])
558                       end
559                     
560                       // Generating resets for lc_aon
561                       // Power Domains: ['Aon']
562                       // Shadowed: False
563                       rstmgr_leaf_rst #(
564                         .SecCheck(SecCheck),
565                         .SecMaxSyncDelay(SecMaxSyncDelay),
566                         .SwRstReq(1'b0)
567                       ) u_daon_lc_aon (
568                         .clk_i,
569                         .rst_ni,
570                         .leaf_clk_i(clk_aon_i),
571                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
572                         .sw_rst_req_ni(1'b1),
573                         .scan_rst_ni,
574                         .scanmode_i,
575                         .rst_en_o(rst_en_o.lc_aon[DomainAonSel]),
576                         .leaf_rst_o(resets_o.rst_lc_aon_n[DomainAonSel]),
577                         .err_o(cnsty_chk_errs[6][DomainAonSel]),
578                         .fsm_err_o(fsm_errs[6][DomainAonSel])
579                       );
580                     
581                       if (SecCheck) begin : gen_daon_lc_aon_assert
582                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
583                         DAonLcAonFsmCheck_A,
584                         u_daon_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs,
585                         alert_tx_o[0])
586                       end
587                       assign resets_o.rst_lc_aon_n[Domain0Sel] = '0;
588                       assign cnsty_chk_errs[6][Domain0Sel] = '0;
589                       assign fsm_errs[6][Domain0Sel] = '0;
590                       assign rst_en_o.lc_aon[Domain0Sel] = MuBi4True;
591                       assign shadow_cnsty_chk_errs[6] = '0;
592                       assign shadow_fsm_errs[6] = '0;
593                     
594                       // Generating resets for lc_io
595                       // Power Domains: ['Aon', '0']
596                       // Shadowed: False
597                       rstmgr_leaf_rst #(
598                         .SecCheck(SecCheck),
599                         .SecMaxSyncDelay(SecMaxSyncDelay),
600                         .SwRstReq(1'b0)
601                       ) u_daon_lc_io (
602                         .clk_i,
603                         .rst_ni,
604                         .leaf_clk_i(clk_io_i),
605                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
606                         .sw_rst_req_ni(1'b1),
607                         .scan_rst_ni,
608                         .scanmode_i,
609                         .rst_en_o(rst_en_o.lc_io[DomainAonSel]),
610                         .leaf_rst_o(resets_o.rst_lc_io_n[DomainAonSel]),
611                         .err_o(cnsty_chk_errs[7][DomainAonSel]),
612                         .fsm_err_o(fsm_errs[7][DomainAonSel])
613                       );
614                     
615                       if (SecCheck) begin : gen_daon_lc_io_assert
616                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
617                         DAonLcIoFsmCheck_A,
618                         u_daon_lc_io.gen_rst_chk.u_rst_chk.u_state_regs,
619                         alert_tx_o[0])
620                       end
621                       rstmgr_leaf_rst #(
622                         .SecCheck(SecCheck),
623                         .SecMaxSyncDelay(SecMaxSyncDelay),
624                         .SwRstReq(1'b0)
625                       ) u_d0_lc_io (
626                         .clk_i,
627                         .rst_ni,
628                         .leaf_clk_i(clk_io_i),
629                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
630                         .sw_rst_req_ni(1'b1),
631                         .scan_rst_ni,
632                         .scanmode_i,
633                         .rst_en_o(rst_en_o.lc_io[Domain0Sel]),
634                         .leaf_rst_o(resets_o.rst_lc_io_n[Domain0Sel]),
635                         .err_o(cnsty_chk_errs[7][Domain0Sel]),
636                         .fsm_err_o(fsm_errs[7][Domain0Sel])
637                       );
638                     
639                       if (SecCheck) begin : gen_d0_lc_io_assert
640                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
641                         D0LcIoFsmCheck_A,
642                         u_d0_lc_io.gen_rst_chk.u_rst_chk.u_state_regs,
643                         alert_tx_o[0])
644                       end
645                       assign shadow_cnsty_chk_errs[7] = '0;
646                       assign shadow_fsm_errs[7] = '0;
647                     
648                       // Generating resets for lc_io_div2
649                       // Power Domains: ['Aon', '0']
650                       // Shadowed: False
651                       rstmgr_leaf_rst #(
652                         .SecCheck(SecCheck),
653                         .SecMaxSyncDelay(SecMaxSyncDelay),
654                         .SwRstReq(1'b0)
655                       ) u_daon_lc_io_div2 (
656                         .clk_i,
657                         .rst_ni,
658                         .leaf_clk_i(clk_io_div2_i),
659                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
660                         .sw_rst_req_ni(1'b1),
661                         .scan_rst_ni,
662                         .scanmode_i,
663                         .rst_en_o(rst_en_o.lc_io_div2[DomainAonSel]),
664                         .leaf_rst_o(resets_o.rst_lc_io_div2_n[DomainAonSel]),
665                         .err_o(cnsty_chk_errs[8][DomainAonSel]),
666                         .fsm_err_o(fsm_errs[8][DomainAonSel])
667                       );
668                     
669                       if (SecCheck) begin : gen_daon_lc_io_div2_assert
670                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
671                         DAonLcIoDiv2FsmCheck_A,
672                         u_daon_lc_io_div2.gen_rst_chk.u_rst_chk.u_state_regs,
673                         alert_tx_o[0])
674                       end
675                       rstmgr_leaf_rst #(
676                         .SecCheck(SecCheck),
677                         .SecMaxSyncDelay(SecMaxSyncDelay),
678                         .SwRstReq(1'b0)
679                       ) u_d0_lc_io_div2 (
680                         .clk_i,
681                         .rst_ni,
682                         .leaf_clk_i(clk_io_div2_i),
683                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
684                         .sw_rst_req_ni(1'b1),
685                         .scan_rst_ni,
686                         .scanmode_i,
687                         .rst_en_o(rst_en_o.lc_io_div2[Domain0Sel]),
688                         .leaf_rst_o(resets_o.rst_lc_io_div2_n[Domain0Sel]),
689                         .err_o(cnsty_chk_errs[8][Domain0Sel]),
690                         .fsm_err_o(fsm_errs[8][Domain0Sel])
691                       );
692                     
693                       if (SecCheck) begin : gen_d0_lc_io_div2_assert
694                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
695                         D0LcIoDiv2FsmCheck_A,
696                         u_d0_lc_io_div2.gen_rst_chk.u_rst_chk.u_state_regs,
697                         alert_tx_o[0])
698                       end
699                       assign shadow_cnsty_chk_errs[8] = '0;
700                       assign shadow_fsm_errs[8] = '0;
701                     
702                       // Generating resets for lc_io_div4
703                       // Power Domains: ['0', 'Aon']
704                       // Shadowed: True
705                       rstmgr_leaf_rst #(
706                         .SecCheck(0),
707                         .SecMaxSyncDelay(SecMaxSyncDelay),
708                         .SwRstReq(1'b0)
709                       ) u_daon_lc_io_div4 (
710                         .clk_i,
711                         .rst_ni,
712                         .leaf_clk_i(clk_io_div4_i),
713                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
714                         .sw_rst_req_ni(1'b1),
715                         .scan_rst_ni,
716                         .scanmode_i,
717                         .rst_en_o(rst_en_o.lc_io_div4[DomainAonSel]),
718                         .leaf_rst_o(resets_o.rst_lc_io_div4_n[DomainAonSel]),
719                         .err_o(cnsty_chk_errs[9][DomainAonSel]),
720                         .fsm_err_o(fsm_errs[9][DomainAonSel])
721                       );
722                     
723                       rstmgr_leaf_rst #(
724                         .SecCheck(0),
725                         .SecMaxSyncDelay(SecMaxSyncDelay),
726                         .SwRstReq(1'b0)
727                       ) u_d0_lc_io_div4 (
728                         .clk_i,
729                         .rst_ni,
730                         .leaf_clk_i(clk_io_div4_i),
731                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
732                         .sw_rst_req_ni(1'b1),
733                         .scan_rst_ni,
734                         .scanmode_i,
735                         .rst_en_o(rst_en_o.lc_io_div4[Domain0Sel]),
736                         .leaf_rst_o(resets_o.rst_lc_io_div4_n[Domain0Sel]),
737                         .err_o(cnsty_chk_errs[9][Domain0Sel]),
738                         .fsm_err_o(fsm_errs[9][Domain0Sel])
739                       );
740                     
741                       rstmgr_leaf_rst #(
742                         .SecCheck(0),
743                         .SecMaxSyncDelay(SecMaxSyncDelay),
744                         .SwRstReq(1'b0)
745                       ) u_daon_lc_io_div4_shadowed (
746                         .clk_i,
747                         .rst_ni,
748                         .leaf_clk_i(clk_io_div4_i),
749                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
750                         .sw_rst_req_ni(1'b1),
751                         .scan_rst_ni,
752                         .scanmode_i,
753                         .rst_en_o(rst_en_o.lc_io_div4_shadowed[DomainAonSel]),
754                         .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[DomainAonSel]),
755                         .err_o(shadow_cnsty_chk_errs[9][DomainAonSel]),
756                         .fsm_err_o(shadow_fsm_errs[9][DomainAonSel])
757                       );
758                     
759                       rstmgr_leaf_rst #(
760                         .SecCheck(0),
761                         .SecMaxSyncDelay(SecMaxSyncDelay),
762                         .SwRstReq(1'b0)
763                       ) u_d0_lc_io_div4_shadowed (
764                         .clk_i,
765                         .rst_ni,
766                         .leaf_clk_i(clk_io_div4_i),
767                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
768                         .sw_rst_req_ni(1'b1),
769                         .scan_rst_ni,
770                         .scanmode_i,
771                         .rst_en_o(rst_en_o.lc_io_div4_shadowed[Domain0Sel]),
772                         .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[Domain0Sel]),
773                         .err_o(shadow_cnsty_chk_errs[9][Domain0Sel]),
774                         .fsm_err_o(shadow_fsm_errs[9][Domain0Sel])
775                       );
776                     
777                     
778                       // Generating resets for lc_usb
779                       // Power Domains: ['Aon', '0']
780                       // Shadowed: False
781                       rstmgr_leaf_rst #(
782                         .SecCheck(SecCheck),
783                         .SecMaxSyncDelay(SecMaxSyncDelay),
784                         .SwRstReq(1'b0)
785                       ) u_daon_lc_usb (
786                         .clk_i,
787                         .rst_ni,
788                         .leaf_clk_i(clk_usb_i),
789                         .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
790                         .sw_rst_req_ni(1'b1),
791                         .scan_rst_ni,
792                         .scanmode_i,
793                         .rst_en_o(rst_en_o.lc_usb[DomainAonSel]),
794                         .leaf_rst_o(resets_o.rst_lc_usb_n[DomainAonSel]),
795                         .err_o(cnsty_chk_errs[10][DomainAonSel]),
796                         .fsm_err_o(fsm_errs[10][DomainAonSel])
797                       );
798                     
799                       if (SecCheck) begin : gen_daon_lc_usb_assert
800                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
801                         DAonLcUsbFsmCheck_A,
802                         u_daon_lc_usb.gen_rst_chk.u_rst_chk.u_state_regs,
803                         alert_tx_o[0])
804                       end
805                       rstmgr_leaf_rst #(
806                         .SecCheck(SecCheck),
807                         .SecMaxSyncDelay(SecMaxSyncDelay),
808                         .SwRstReq(1'b0)
809                       ) u_d0_lc_usb (
810                         .clk_i,
811                         .rst_ni,
812                         .leaf_clk_i(clk_usb_i),
813                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
814                         .sw_rst_req_ni(1'b1),
815                         .scan_rst_ni,
816                         .scanmode_i,
817                         .rst_en_o(rst_en_o.lc_usb[Domain0Sel]),
818                         .leaf_rst_o(resets_o.rst_lc_usb_n[Domain0Sel]),
819                         .err_o(cnsty_chk_errs[10][Domain0Sel]),
820                         .fsm_err_o(fsm_errs[10][Domain0Sel])
821                       );
822                     
823                       if (SecCheck) begin : gen_d0_lc_usb_assert
824                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
825                         D0LcUsbFsmCheck_A,
826                         u_d0_lc_usb.gen_rst_chk.u_rst_chk.u_state_regs,
827                         alert_tx_o[0])
828                       end
829                       assign shadow_cnsty_chk_errs[10] = '0;
830                       assign shadow_fsm_errs[10] = '0;
831                     
832                       // Generating resets for sys
833                       // Power Domains: ['0']
834                       // Shadowed: False
835                       assign resets_o.rst_sys_n[DomainAonSel] = '0;
836                       assign cnsty_chk_errs[11][DomainAonSel] = '0;
837                       assign fsm_errs[11][DomainAonSel] = '0;
838                       assign rst_en_o.sys[DomainAonSel] = MuBi4True;
839                       rstmgr_leaf_rst #(
840                         .SecCheck(SecCheck),
841                         .SecMaxSyncDelay(SecMaxSyncDelay),
842                         .SwRstReq(1'b0)
843                       ) u_d0_sys (
844                         .clk_i,
845                         .rst_ni,
846                         .leaf_clk_i(clk_main_i),
847                         .parent_rst_ni(rst_sys_src_n[Domain0Sel]),
848                         .sw_rst_req_ni(1'b1),
849                         .scan_rst_ni,
850                         .scanmode_i,
851                         .rst_en_o(rst_en_o.sys[Domain0Sel]),
852                         .leaf_rst_o(resets_o.rst_sys_n[Domain0Sel]),
853                         .err_o(cnsty_chk_errs[11][Domain0Sel]),
854                         .fsm_err_o(fsm_errs[11][Domain0Sel])
855                       );
856                     
857                       if (SecCheck) begin : gen_d0_sys_assert
858                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
859                         D0SysFsmCheck_A,
860                         u_d0_sys.gen_rst_chk.u_rst_chk.u_state_regs,
861                         alert_tx_o[0])
862                       end
863                       assign shadow_cnsty_chk_errs[11] = '0;
864                       assign shadow_fsm_errs[11] = '0;
865                     
866                       // Generating resets for sys_io_div4
867                       // Power Domains: ['Aon']
868                       // Shadowed: False
869                       rstmgr_leaf_rst #(
870                         .SecCheck(SecCheck),
871                         .SecMaxSyncDelay(SecMaxSyncDelay),
872                         .SwRstReq(1'b0)
873                       ) u_daon_sys_io_div4 (
874                         .clk_i,
875                         .rst_ni,
876                         .leaf_clk_i(clk_io_div4_i),
877                         .parent_rst_ni(rst_sys_src_n[DomainAonSel]),
878                         .sw_rst_req_ni(1'b1),
879                         .scan_rst_ni,
880                         .scanmode_i,
881                         .rst_en_o(rst_en_o.sys_io_div4[DomainAonSel]),
882                         .leaf_rst_o(resets_o.rst_sys_io_div4_n[DomainAonSel]),
883                         .err_o(cnsty_chk_errs[12][DomainAonSel]),
884                         .fsm_err_o(fsm_errs[12][DomainAonSel])
885                       );
886                     
887                       if (SecCheck) begin : gen_daon_sys_io_div4_assert
888                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
889                         DAonSysIoDiv4FsmCheck_A,
890                         u_daon_sys_io_div4.gen_rst_chk.u_rst_chk.u_state_regs,
891                         alert_tx_o[0])
892                       end
893                       assign resets_o.rst_sys_io_div4_n[Domain0Sel] = '0;
894                       assign cnsty_chk_errs[12][Domain0Sel] = '0;
895                       assign fsm_errs[12][Domain0Sel] = '0;
896                       assign rst_en_o.sys_io_div4[Domain0Sel] = MuBi4True;
897                       assign shadow_cnsty_chk_errs[12] = '0;
898                       assign shadow_fsm_errs[12] = '0;
899                     
900                       // Generating resets for spi_device
901                       // Power Domains: ['0']
902                       // Shadowed: False
903                       assign resets_o.rst_spi_device_n[DomainAonSel] = '0;
904                       assign cnsty_chk_errs[13][DomainAonSel] = '0;
905                       assign fsm_errs[13][DomainAonSel] = '0;
906                       assign rst_en_o.spi_device[DomainAonSel] = MuBi4True;
907                       rstmgr_leaf_rst #(
908                         .SecCheck(SecCheck),
909                         .SecMaxSyncDelay(SecMaxSyncDelay),
910                         .SwRstReq(1'b1)
911                       ) u_d0_spi_device (
912                         .clk_i,
913                         .rst_ni,
914                         .leaf_clk_i(clk_io_div4_i),
915                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
916                         .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_DEVICE].q),
917                         .scan_rst_ni,
918                         .scanmode_i,
919                         .rst_en_o(rst_en_o.spi_device[Domain0Sel]),
920                         .leaf_rst_o(resets_o.rst_spi_device_n[Domain0Sel]),
921                         .err_o(cnsty_chk_errs[13][Domain0Sel]),
922                         .fsm_err_o(fsm_errs[13][Domain0Sel])
923                       );
924                     
925                       if (SecCheck) begin : gen_d0_spi_device_assert
926                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
927                         D0SpiDeviceFsmCheck_A,
928                         u_d0_spi_device.gen_rst_chk.u_rst_chk.u_state_regs,
929                         alert_tx_o[0])
930                       end
931                       assign shadow_cnsty_chk_errs[13] = '0;
932                       assign shadow_fsm_errs[13] = '0;
933                     
934                       // Generating resets for spi_host0
935                       // Power Domains: ['0']
936                       // Shadowed: False
937                       assign resets_o.rst_spi_host0_n[DomainAonSel] = '0;
938                       assign cnsty_chk_errs[14][DomainAonSel] = '0;
939                       assign fsm_errs[14][DomainAonSel] = '0;
940                       assign rst_en_o.spi_host0[DomainAonSel] = MuBi4True;
941                       rstmgr_leaf_rst #(
942                         .SecCheck(SecCheck),
943                         .SecMaxSyncDelay(SecMaxSyncDelay),
944                         .SwRstReq(1'b1)
945                       ) u_d0_spi_host0 (
946                         .clk_i,
947                         .rst_ni,
948                         .leaf_clk_i(clk_io_i),
949                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
950                         .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST0].q),
951                         .scan_rst_ni,
952                         .scanmode_i,
953                         .rst_en_o(rst_en_o.spi_host0[Domain0Sel]),
954                         .leaf_rst_o(resets_o.rst_spi_host0_n[Domain0Sel]),
955                         .err_o(cnsty_chk_errs[14][Domain0Sel]),
956                         .fsm_err_o(fsm_errs[14][Domain0Sel])
957                       );
958                     
959                       if (SecCheck) begin : gen_d0_spi_host0_assert
960                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
961                         D0SpiHost0FsmCheck_A,
962                         u_d0_spi_host0.gen_rst_chk.u_rst_chk.u_state_regs,
963                         alert_tx_o[0])
964                       end
965                       assign shadow_cnsty_chk_errs[14] = '0;
966                       assign shadow_fsm_errs[14] = '0;
967                     
968                       // Generating resets for spi_host1
969                       // Power Domains: ['0']
970                       // Shadowed: False
971                       assign resets_o.rst_spi_host1_n[DomainAonSel] = '0;
972                       assign cnsty_chk_errs[15][DomainAonSel] = '0;
973                       assign fsm_errs[15][DomainAonSel] = '0;
974                       assign rst_en_o.spi_host1[DomainAonSel] = MuBi4True;
975                       rstmgr_leaf_rst #(
976                         .SecCheck(SecCheck),
977                         .SecMaxSyncDelay(SecMaxSyncDelay),
978                         .SwRstReq(1'b1)
979                       ) u_d0_spi_host1 (
980                         .clk_i,
981                         .rst_ni,
982                         .leaf_clk_i(clk_io_div2_i),
983                         .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
984                         .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST1].q),
985                         .scan_rst_ni,
986                         .scanmode_i,
987                         .rst_en_o(rst_en_o.spi_host1[Domain0Sel]),
988                         .leaf_rst_o(resets_o.rst_spi_host1_n[Domain0Sel]),
989                         .err_o(cnsty_chk_errs[15][Domain0Sel]),
990                         .fsm_err_o(fsm_errs[15][Domain0Sel])
991                       );
992                     
993                       if (SecCheck) begin : gen_d0_spi_host1_assert
994                       `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
995                         D0SpiHost1FsmCheck_A,
996                         u_d0_spi_host1.gen_rst_chk.u_rst_chk.u_state_regs,
997                         alert_tx_o[0])
998                       end
999                       assign shadow_cnsty_chk_errs[15] = '0;
1000                      assign shadow_fsm_errs[15] = '0;
1001                    
1002                      // Generating resets for usb
1003                      // Power Domains: ['0']
1004                      // Shadowed: False
1005                      assign resets_o.rst_usb_n[DomainAonSel] = '0;
1006                      assign cnsty_chk_errs[16][DomainAonSel] = '0;
1007                      assign fsm_errs[16][DomainAonSel] = '0;
1008                      assign rst_en_o.usb[DomainAonSel] = MuBi4True;
1009                      rstmgr_leaf_rst #(
1010                        .SecCheck(SecCheck),
1011                        .SecMaxSyncDelay(SecMaxSyncDelay),
1012                        .SwRstReq(1'b1)
1013                      ) u_d0_usb (
1014                        .clk_i,
1015                        .rst_ni,
1016                        .leaf_clk_i(clk_usb_i),
1017                        .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
1018                        .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[USB].q),
1019                        .scan_rst_ni,
1020                        .scanmode_i,
1021                        .rst_en_o(rst_en_o.usb[Domain0Sel]),
1022                        .leaf_rst_o(resets_o.rst_usb_n[Domain0Sel]),
1023                        .err_o(cnsty_chk_errs[16][Domain0Sel]),
1024                        .fsm_err_o(fsm_errs[16][Domain0Sel])
1025                      );
1026                    
1027                      if (SecCheck) begin : gen_d0_usb_assert
1028                      `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
1029                        D0UsbFsmCheck_A,
1030                        u_d0_usb.gen_rst_chk.u_rst_chk.u_state_regs,
1031                        alert_tx_o[0])
1032                      end
1033                      assign shadow_cnsty_chk_errs[16] = '0;
1034                      assign shadow_fsm_errs[16] = '0;
1035                    
1036                      // Generating resets for usb_aon
1037                      // Power Domains: ['0']
1038                      // Shadowed: False
1039                      assign resets_o.rst_usb_aon_n[DomainAonSel] = '0;
1040                      assign cnsty_chk_errs[17][DomainAonSel] = '0;
1041                      assign fsm_errs[17][DomainAonSel] = '0;
1042                      assign rst_en_o.usb_aon[DomainAonSel] = MuBi4True;
1043                      rstmgr_leaf_rst #(
1044                        .SecCheck(SecCheck),
1045                        .SecMaxSyncDelay(SecMaxSyncDelay),
1046                        .SwRstReq(1'b1)
1047                      ) u_d0_usb_aon (
1048                        .clk_i,
1049                        .rst_ni,
1050                        .leaf_clk_i(clk_aon_i),
1051                        .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
1052                        .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[USB_AON].q),
1053                        .scan_rst_ni,
1054                        .scanmode_i,
1055                        .rst_en_o(rst_en_o.usb_aon[Domain0Sel]),
1056                        .leaf_rst_o(resets_o.rst_usb_aon_n[Domain0Sel]),
1057                        .err_o(cnsty_chk_errs[17][Domain0Sel]),
1058                        .fsm_err_o(fsm_errs[17][Domain0Sel])
1059                      );
1060                    
1061                      if (SecCheck) begin : gen_d0_usb_aon_assert
1062                      `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
1063                        D0UsbAonFsmCheck_A,
1064                        u_d0_usb_aon.gen_rst_chk.u_rst_chk.u_state_regs,
1065                        alert_tx_o[0])
1066                      end
1067                      assign shadow_cnsty_chk_errs[17] = '0;
1068                      assign shadow_fsm_errs[17] = '0;
1069                    
1070                      // Generating resets for i2c0
1071                      // Power Domains: ['0']
1072                      // Shadowed: False
1073                      assign resets_o.rst_i2c0_n[DomainAonSel] = '0;
1074                      assign cnsty_chk_errs[18][DomainAonSel] = '0;
1075                      assign fsm_errs[18][DomainAonSel] = '0;
1076                      assign rst_en_o.i2c0[DomainAonSel] = MuBi4True;
1077                      rstmgr_leaf_rst #(
1078                        .SecCheck(SecCheck),
1079                        .SecMaxSyncDelay(SecMaxSyncDelay),
1080                        .SwRstReq(1'b1)
1081                      ) u_d0_i2c0 (
1082                        .clk_i,
1083                        .rst_ni,
1084                        .leaf_clk_i(clk_io_div4_i),
1085                        .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
1086                        .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C0].q),
1087                        .scan_rst_ni,
1088                        .scanmode_i,
1089                        .rst_en_o(rst_en_o.i2c0[Domain0Sel]),
1090                        .leaf_rst_o(resets_o.rst_i2c0_n[Domain0Sel]),
1091                        .err_o(cnsty_chk_errs[18][Domain0Sel]),
1092                        .fsm_err_o(fsm_errs[18][Domain0Sel])
1093                      );
1094                    
1095                      if (SecCheck) begin : gen_d0_i2c0_assert
1096                      `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
1097                        D0I2c0FsmCheck_A,
1098                        u_d0_i2c0.gen_rst_chk.u_rst_chk.u_state_regs,
1099                        alert_tx_o[0])
1100                      end
1101                      assign shadow_cnsty_chk_errs[18] = '0;
1102                      assign shadow_fsm_errs[18] = '0;
1103                    
1104                      // Generating resets for i2c1
1105                      // Power Domains: ['0']
1106                      // Shadowed: False
1107                      assign resets_o.rst_i2c1_n[DomainAonSel] = '0;
1108                      assign cnsty_chk_errs[19][DomainAonSel] = '0;
1109                      assign fsm_errs[19][DomainAonSel] = '0;
1110                      assign rst_en_o.i2c1[DomainAonSel] = MuBi4True;
1111                      rstmgr_leaf_rst #(
1112                        .SecCheck(SecCheck),
1113                        .SecMaxSyncDelay(SecMaxSyncDelay),
1114                        .SwRstReq(1'b1)
1115                      ) u_d0_i2c1 (
1116                        .clk_i,
1117                        .rst_ni,
1118                        .leaf_clk_i(clk_io_div4_i),
1119                        .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
1120                        .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C1].q),
1121                        .scan_rst_ni,
1122                        .scanmode_i,
1123                        .rst_en_o(rst_en_o.i2c1[Domain0Sel]),
1124                        .leaf_rst_o(resets_o.rst_i2c1_n[Domain0Sel]),
1125                        .err_o(cnsty_chk_errs[19][Domain0Sel]),
1126                        .fsm_err_o(fsm_errs[19][Domain0Sel])
1127                      );
1128                    
1129                      if (SecCheck) begin : gen_d0_i2c1_assert
1130                      `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
1131                        D0I2c1FsmCheck_A,
1132                        u_d0_i2c1.gen_rst_chk.u_rst_chk.u_state_regs,
1133                        alert_tx_o[0])
1134                      end
1135                      assign shadow_cnsty_chk_errs[19] = '0;
1136                      assign shadow_fsm_errs[19] = '0;
1137                    
1138                      // Generating resets for i2c2
1139                      // Power Domains: ['0']
1140                      // Shadowed: False
1141                      assign resets_o.rst_i2c2_n[DomainAonSel] = '0;
1142                      assign cnsty_chk_errs[20][DomainAonSel] = '0;
1143                      assign fsm_errs[20][DomainAonSel] = '0;
1144                      assign rst_en_o.i2c2[DomainAonSel] = MuBi4True;
1145                      rstmgr_leaf_rst #(
1146                        .SecCheck(SecCheck),
1147                        .SecMaxSyncDelay(SecMaxSyncDelay),
1148                        .SwRstReq(1'b1)
1149                      ) u_d0_i2c2 (
1150                        .clk_i,
1151                        .rst_ni,
1152                        .leaf_clk_i(clk_io_div4_i),
1153                        .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
1154                        .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C2].q),
1155                        .scan_rst_ni,
1156                        .scanmode_i,
1157                        .rst_en_o(rst_en_o.i2c2[Domain0Sel]),
1158                        .leaf_rst_o(resets_o.rst_i2c2_n[Domain0Sel]),
1159                        .err_o(cnsty_chk_errs[20][Domain0Sel]),
1160                        .fsm_err_o(fsm_errs[20][Domain0Sel])
1161                      );
1162                    
1163                      if (SecCheck) begin : gen_d0_i2c2_assert
1164                      `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
1165                        D0I2c2FsmCheck_A,
1166                        u_d0_i2c2.gen_rst_chk.u_rst_chk.u_state_regs,
1167                        alert_tx_o[0])
1168                      end
1169                      assign shadow_cnsty_chk_errs[20] = '0;
1170                      assign shadow_fsm_errs[20] = '0;
1171                    
1172                    
1173                      ////////////////////////////////////////////////////
1174                      // Reset info construction                        //
1175                      ////////////////////////////////////////////////////
1176                    
1177                      logic rst_hw_req;
1178                      logic rst_low_power;
1179                      logic pwrmgr_rst_req;
1180                    
1181                      // there is a valid reset request from pwrmgr
1182       1/1            assign pwrmgr_rst_req = |pwr_i.rst_lc_req || |pwr_i.rst_sys_req;
           Tests:       T1 T2 T3 
1183                    
1184                      // a reset reason is only valid if the related processing element is also reset.
1185                      // In the future, if ever there are multiple processing elements, this code here
1186                      // must be updated to account for each individual core.
1187       1/1            assign rst_hw_req    = pwrmgr_rst_req &
           Tests:       T1 T2 T3 
1188                                             (pwr_i.reset_cause == pwrmgr_pkg::HwReq);
1189       1/1            assign rst_low_power = pwrmgr_rst_req &
           Tests:       T1 T2 T3 
1190                                             (pwr_i.reset_cause == pwrmgr_pkg::LowPwrEntry);
1191                    
1192                      // software initiated reset request
1193       1/1            assign sw_rst_req_o = prim_mubi_pkg::mubi4_t'(reg2hw.reset_req.q);
           Tests:       T1 T3 T8 
1194                    
1195                      // when pwrmgr reset request is received (reset is imminent), clear software
1196                      // request so we are not in an infinite reset loop.
1197       1/1            assign hw2reg.reset_req.de = pwrmgr_rst_req;
           Tests:       T1 T2 T3 
1198                      assign hw2reg.reset_req.d  = prim_mubi_pkg::MuBi4False;
1199                    
1200                      // Only sw is allowed to clear a reset reason, hw is only allowed to set it.
1201                      assign hw2reg.reset_info.low_power_exit.d  = 1'b1;
1202       1/1            assign hw2reg.reset_info.low_power_exit.de = rst_low_power;
           Tests:       T1 T3 T8 
1203                    
1204                      // software issued request triggers the same response as hardware, although it is
1205                      // accounted for differently.
1206       1/1            assign hw2reg.reset_info.sw_reset.d = prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_o) |
           Tests:       T1 T3 T8 
1207                                                            reg2hw.reset_info.sw_reset.q;
1208       1/1            assign hw2reg.reset_info.sw_reset.de = rst_hw_req;
           Tests:       T1 T3 T5 
1209                    
1210                      // HW reset requests most likely will be multi-bit, so OR in whatever reasons
1211                      // that are already set.
1212       1/1            assign hw2reg.reset_info.hw_req.d  = pwr_i.rstreqs |
           Tests:       T1 T3 T5 
1213                                                           reg2hw.reset_info.hw_req.q;
1214       1/1            assign hw2reg.reset_info.hw_req.de = rst_hw_req;
           Tests:       T1 T3 T5 
1215                    
1216                      ////////////////////////////////////////////////////
1217                      // Crash info capture                             //
1218                      ////////////////////////////////////////////////////
1219                    
1220                      logic dump_capture;
1221       1/1            assign dump_capture =  rst_hw_req | rst_low_power;
           Tests:       T1 T3 T5 
1222                    
1223                      // halt dump capture once we hit particular conditions
1224                      logic dump_capture_halt;
1225       1/1            assign dump_capture_halt = rst_hw_req;
           Tests:       T1 T3 T5 
1226                    
1227                      rstmgr_crash_info #(
1228                        .CrashDumpWidth($bits(alert_pkg::alert_crashdump_t))
1229                      ) u_alert_info (
1230                        .clk_i(clk_por_i),
1231                        .rst_ni(rst_por_ni),
1232                        .dump_i(alert_dump_i),
1233                        .dump_capture_i(dump_capture & reg2hw.alert_info_ctrl.en.q),
1234                        .slot_sel_i(reg2hw.alert_info_ctrl.index.q),
1235                        .slots_cnt_o(hw2reg.alert_info_attr.d),
1236                        .slot_o(hw2reg.alert_info.d)
1237                      );
1238                    
1239                      rstmgr_crash_info #(
1240                        .CrashDumpWidth($bits(rv_core_ibex_pkg::cpu_crash_dump_t))
1241                      ) u_cpu_info (
1242                        .clk_i(clk_por_i),
1243                        .rst_ni(rst_por_ni),
1244                        .dump_i(cpu_dump_i),
1245                        .dump_capture_i(dump_capture & reg2hw.cpu_info_ctrl.en.q),
1246                        .slot_sel_i(reg2hw.cpu_info_ctrl.index.q),
1247                        .slots_cnt_o(hw2reg.cpu_info_attr.d),
1248                        .slot_o(hw2reg.cpu_info.d)
1249                      );
1250                    
1251                      // once dump is captured, no more information is captured until
1252                      // re-enabled by software.
1253                      assign hw2reg.alert_info_ctrl.en.d  = 1'b0;
1254       1/1            assign hw2reg.alert_info_ctrl.en.de = dump_capture_halt;
           Tests:       T1 T3 T5 
1255                      assign hw2reg.cpu_info_ctrl.en.d  = 1'b0;
1256       1/1            assign hw2reg.cpu_info_ctrl.en.de = dump_capture_halt;
           Tests:       T1 T3 T5 

---

Cond Coverage for Module : rstmgr

	Total	Covered	Percent
Conditions	56	55	98.21
Logical	56	55	98.21
Non-Logical	0	0
Event	0	0

 LINE       55
 SUB-EXPRESSION (rst_en_o.i2c2[1] == MuBi4True)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.i2c1[1] == MuBi4True)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.i2c0[1] == MuBi4True)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.usb_aon[1] == MuBi4True)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.usb[1] == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.spi_host1[1] == MuBi4True)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.spi_host0[1] == MuBi4True)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       55
 SUB-EXPRESSION (rst_en_o.spi_device[1] == MuBi4True)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (rst_por_aon_n[rstmgr_pkg::DomainAonSel] & por_n_i[1])
             -------------------1-------------------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       198
 EXPRESSION (((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T24,T73
1	0	Covered	T9,T24,T73

 LINE       201
 EXPRESSION (((|fsm_errs)) || ((|shadow_fsm_errs)))
             ------1------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T74,T75
1	0	Covered	T54,T74,T75

 LINE       208
 EXPRESSION (reg2hw.err_code.reg_intg_err.q | ((|reg2hw.err_code.fsm_err.q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T74,T75
1	0	Covered	T54,T74,T75

 LINE       213
 SUB-EXPRESSION (reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T57,T81
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T57,T81

 LINE       213
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T57,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T57,T81

 LINE       1182
 EXPRESSION (((|pwr_i.rst_lc_req)) || ((|pwr_i.rst_sys_req)))
             ----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       1187
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == HwReq))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       1187
 SUB-EXPRESSION (pwr_i.reset_cause == HwReq)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       1189
 EXPRESSION (pwrmgr_rst_req & (pwr_i.reset_cause == LowPwrEntry))
             -------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       1189
 SUB-EXPRESSION (pwr_i.reset_cause == LowPwrEntry)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       1221
 EXPRESSION (rst_hw_req | rst_low_power)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       1229
 EXPRESSION (dump_capture & reg2hw.alert_info_ctrl.en.q)
             ------1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       1241
 EXPRESSION (dump_capture & reg2hw.cpu_info_ctrl.en.q)
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

---

Toggle Coverage for Module : rstmgr

	Total	Covered	Percent
Totals	68	68	100.00
Total Bits	1418	1418	100.00
Total Bits 0->1	709	709	100.00
Total Bits 1->0	709	709	100.00

Ports	68	68	100.00
Port Bits	1418	1418	100.00
Port Bits 0->1	709	709	100.00
Port Bits 1->0	709	709	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_div4_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_div2_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_por_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_por_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
por_n_i[1:0]	Yes	Yes	T2,T7,T9	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T10,T66	Yes	T6,T10,T66	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T80	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T57,T81	Yes	T4,T57,T81	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T24,T57	Yes	T4,T24,T57	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T57,T81	Yes	T4,T57,T81	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T9,T24	Yes	T4,T9,T24	OUTPUT
pwr_i.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_i.rstreqs[4:0]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	INPUT
pwr_i.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_i.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_o.rst_sys_src_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_o.rst_lc_src_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sw_rst_req_o[3:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
alert_dump_i.class_esc_cnt[0][0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][1]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][2]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[0][6:3]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][7]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][12:8]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][13]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][14]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][19:15]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][20]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[0][25:21]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][26]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[0][28:27]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][29]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[0][31:30]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][12:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][13]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][19:14]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][20]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[1][21]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][22]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][23]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][30:24]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[1][31]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][6:1]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][8:7]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[2][12:9]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][13]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[2][22:14]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][24:23]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[2][27:25]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][28]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[2][29]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[2][30]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_esc_cnt[2][31]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][1]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][12:2]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][13]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][22:14]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][23]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][27:24]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][28]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][30:29]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_esc_cnt[3][31]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_accum_cnt[0][1:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[0][2]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[0][15:3]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[1][0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[1][1]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[1][2]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[1][13:3]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[1][14]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[1][15]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[2][1:0]	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
alert_dump_i.class_accum_cnt[2][2]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[2][7:3]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[2][8]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[2][15:9]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[3][10:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[3][11]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.class_accum_cnt[3][15:12]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.loc_alert_cause[6:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
alert_dump_i.alert_cause[64:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
cpu_dump_i.current.exception_addr[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
cpu_dump_i.current.exception_pc[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T8,T11	INPUT
cpu_dump_i.current.last_data_addr[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T8,T11	INPUT
cpu_dump_i.current.next_pc[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
cpu_dump_i.current.current_pc[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T8,T11	INPUT
cpu_dump_i.prev_exception_addr[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
cpu_dump_i.prev_exception_pc[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T8,T11	INPUT
cpu_dump_i.prev_valid	Yes	Yes	T1,T8,T11	Yes	T1,T8,T11	INPUT
scan_rst_ni	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
resets_o.rst_i2c2_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_i2c1_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_i2c0_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_usb_aon_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_usb_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_host1_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_host0_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_spi_device_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_sys_io_div4_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_sys_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_lc_usb_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_io_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_aon_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_lc_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
resets_o.rst_por_usb_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_div4_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_div2_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_io_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_n[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
resets_o.rst_por_aon_n[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rstmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	34	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	34	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnownO_A	11043460	6202425	0	0
FpvSecCmRegWeOnehotCheck_A	11043460	80	0	0
ParameterMatch_A	505	505	0	0
PwrKnownO_A	11043460	6202425	0	0
ResetsKnownO_A	11043460	6202425	0	0
RstEnKnownO_A	11043460	6202425	0	0
TlAReadyKnownO_A	11043460	6202425	0	0
TlDValidKnownO_A	11043460	6202425	0	0
gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	11043460	80	0	0
gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	11043460	80	0	0
gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	11043460	80	0	0
gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	11043460	80	0	0
gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	11043460	80	0	0
gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	11043460	80	0	0
gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	11043460	80	0	0
gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	11043460	80	0	0
gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	11043460	80	0	0
gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	11043460	80	0	0
gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	11043460	80	0	0
gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	11043460	80	0	0
gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	11043460	80	0	0
gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	11043460	80	0	0
gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	11043460	80	0	0
gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	11043460	80	0	0
gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	11043460	80	0	0
gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	11043460	80	0	0
gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	11043460	80	0	0
gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	11043460	80	0	0
gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	11043460	80	0	0
gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	11043460	80	0	0
gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	11043460	80	0	0
gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	11043460	80	0	0
gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	11043460	80	0	0
gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	11043460	80	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6202425	0	0
T1	2730	1724	0	0
T2	3005	691	0	0
T3	3427	2416	0	0
T4	1538	898	0	0
T5	1794	1092	0	0
T6	2637	1967	0	0
T7	2819	663	0	0
T8	2679	1709	0	0
T9	5310	555	0	0
T10	6499	5856	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

ParameterMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505	505	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

PwrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6202425	0	0
T1	2730	1724	0	0
T2	3005	691	0	0
T3	3427	2416	0	0
T4	1538	898	0	0
T5	1794	1092	0	0
T6	2637	1967	0	0
T7	2819	663	0	0
T8	2679	1709	0	0
T9	5310	555	0	0
T10	6499	5856	0	0

ResetsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6202425	0	0
T1	2730	1724	0	0
T2	3005	691	0	0
T3	3427	2416	0	0
T4	1538	898	0	0
T5	1794	1092	0	0
T6	2637	1967	0	0
T7	2819	663	0	0
T8	2679	1709	0	0
T9	5310	555	0	0
T10	6499	5856	0	0

RstEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6202425	0	0
T1	2730	1724	0	0
T2	3005	691	0	0
T3	3427	2416	0	0
T4	1538	898	0	0
T5	1794	1092	0	0
T6	2637	1967	0	0
T7	2819	663	0	0
T8	2679	1709	0	0
T9	5310	555	0	0
T10	6499	5856	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6202425	0	0
T1	2730	1724	0	0
T2	3005	691	0	0
T3	3427	2416	0	0
T4	1538	898	0	0
T5	1794	1092	0	0
T6	2637	1967	0	0
T7	2819	663	0	0
T8	2679	1709	0	0
T9	5310	555	0	0
T10	6499	5856	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	6202425	0	0
T1	2730	1724	0	0
T2	3005	691	0	0
T3	3427	2416	0	0
T4	1538	898	0	0
T5	1794	1092	0	0
T6	2637	1967	0	0
T7	2819	663	0	0
T8	2679	1709	0	0
T9	5310	555	0	0
T10	6499	5856	0	0

gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0

gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	80	0	0
T17	2387	0	0	0
T54	192881	10	0	0
T55	5938	0	0	0
T56	2682	0	0	0
T74	0	10	0	0
T75	0	20	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	3539	0	0	0
T85	1330	0	0	0
T86	9368	0	0	0
T87	5658	0	0	0
T88	2497	0	0	0
T89	43296	0	0	0