Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T1 T3 T8 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T1 T3 T8 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T11,T13,T72

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52059582	8830	0	0
CascadeEffAonToRstPorAboveRise_A	52059582	8830	0	0
CascadeEffAonToRstPorIoAboveFall_A	49975938	8830	0	0
CascadeEffAonToRstPorIoAboveRise_A	49975938	8830	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24988638	8830	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24988638	8830	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12494304	8830	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12494304	8830	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24988630	8830	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24988630	8830	0	0
CascadeLcToLcAboveFall_A	52059582	21681	0	0
CascadeLcToLcAboveRise_A	52059582	21681	0	0
CascadeLcToLcAonAboveFall_A	1578096	21681	0	0
CascadeLcToLcAonAboveRise_A	1578096	21681	0	0
CascadeLcToLcShadowedAboveFall_A	52059582	21681	0	0
CascadeLcToLcShadowedAboveRise_A	52059582	21681	0	0
CascadePorToAonAboveFall_A	1578096	7057	0	0
CascadeSysToSysAboveFall_A	52059582	21681	0	0
CascadeSysToSysAboveRise_A	52059582	21681	0	0
ScanRstToAonRise_A	1578096	204	0	0
StablePorToAonRise_A	1578096	8830	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11043460	21681	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11043460	21681	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11043460	21681	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11043460	21681	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12494304	21681	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12494304	21681	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11043460	21681	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11043460	21681	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11043460	21681	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11043460	21681	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	8830	0	0
T1	11766	2	0	0
T2	13302	2	0	0
T3	14893	2	0	0
T4	6488	1	0	0
T5	8949	1	0	0
T6	12901	1	0	0
T7	12228	2	0	0
T8	12372	2	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	8830	0	0
T1	11766	2	0	0
T2	13302	2	0	0
T3	14893	2	0	0
T4	6488	1	0	0
T5	8949	1	0	0
T6	12901	1	0	0
T7	12228	2	0	0
T8	12372	2	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	8830	0	0
T1	11294	2	0	0
T2	12768	2	0	0
T3	14294	2	0	0
T4	6229	1	0	0
T5	8591	1	0	0
T6	12386	1	0	0
T7	11739	2	0	0
T8	11883	2	0	0
T9	23417	8	0	0
T10	26073	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	8830	0	0
T1	11294	2	0	0
T2	12768	2	0	0
T3	14294	2	0	0
T4	6229	1	0	0
T5	8591	1	0	0
T6	12386	1	0	0
T7	11739	2	0	0
T8	11883	2	0	0
T9	23417	8	0	0
T10	26073	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	8830	0	0
T1	5642	2	0	0
T2	6384	2	0	0
T3	7147	2	0	0
T4	3114	1	0	0
T5	4295	1	0	0
T6	6193	1	0	0
T7	5869	2	0	0
T8	5939	2	0	0
T9	11708	8	0	0
T10	13036	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	8830	0	0
T1	5642	2	0	0
T2	6384	2	0	0
T3	7147	2	0	0
T4	3114	1	0	0
T5	4295	1	0	0
T6	6193	1	0	0
T7	5869	2	0	0
T8	5939	2	0	0
T9	11708	8	0	0
T10	13036	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	8830	0	0
T1	2822	2	0	0
T2	3191	2	0	0
T3	3574	2	0	0
T4	1556	1	0	0
T5	2146	1	0	0
T6	3095	1	0	0
T7	2934	2	0	0
T8	2969	2	0	0
T9	5853	8	0	0
T10	6516	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	8830	0	0
T1	2822	2	0	0
T2	3191	2	0	0
T3	3574	2	0	0
T4	1556	1	0	0
T5	2146	1	0	0
T6	3095	1	0	0
T7	2934	2	0	0
T8	2969	2	0	0
T9	5853	8	0	0
T10	6516	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	8830	0	0
T1	5646	2	0	0
T2	6384	2	0	0
T3	7148	2	0	0
T4	3113	1	0	0
T5	4295	1	0	0
T6	6192	1	0	0
T7	5869	2	0	0
T8	5939	2	0	0
T9	11706	8	0	0
T10	13036	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	8830	0	0
T1	5646	2	0	0
T2	6384	2	0	0
T3	7148	2	0	0
T4	3113	1	0	0
T5	4295	1	0	0
T6	6192	1	0	0
T7	5869	2	0	0
T8	5939	2	0	0
T9	11706	8	0	0
T10	13036	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	21681	0	0
T1	11766	6	0	0
T2	13302	2	0	0
T3	14893	6	0	0
T4	6488	1	0	0
T5	8949	5	0	0
T6	12901	7	0	0
T7	12228	2	0	0
T8	12372	6	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	21681	0	0
T1	11766	6	0	0
T2	13302	2	0	0
T3	14893	6	0	0
T4	6488	1	0	0
T5	8949	5	0	0
T6	12901	7	0	0
T7	12228	2	0	0
T8	12372	6	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	21681	0	0
T1	352	6	0	0
T2	397	2	0	0
T3	446	6	0	0
T4	194	1	0	0
T5	268	5	0	0
T6	386	7	0	0
T7	365	2	0	0
T8	370	6	0	0
T9	734	8	0	0
T10	814	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	21681	0	0
T1	352	6	0	0
T2	397	2	0	0
T3	446	6	0	0
T4	194	1	0	0
T5	268	5	0	0
T6	386	7	0	0
T7	365	2	0	0
T8	370	6	0	0
T9	734	8	0	0
T10	814	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	21681	0	0
T1	11766	6	0	0
T2	13302	2	0	0
T3	14893	6	0	0
T4	6488	1	0	0
T5	8949	5	0	0
T6	12901	7	0	0
T7	12228	2	0	0
T8	12372	6	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	21681	0	0
T1	11766	6	0	0
T2	13302	2	0	0
T3	14893	6	0	0
T4	6488	1	0	0
T5	8949	5	0	0
T6	12901	7	0	0
T7	12228	2	0	0
T8	12372	6	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	7057	0	0
T1	352	1	0	0
T2	397	11	0	0
T3	446	1	0	0
T4	194	1	0	0
T5	268	1	0	0
T6	386	1	0	0
T7	365	10	0	0
T8	370	1	0	0
T9	734	8	0	0
T10	814	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	21681	0	0
T1	11766	6	0	0
T2	13302	2	0	0
T3	14893	6	0	0
T4	6488	1	0	0
T5	8949	5	0	0
T6	12901	7	0	0
T7	12228	2	0	0
T8	12372	6	0	0
T9	24393	8	0	0
T10	27160	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	21681	0	0
T1	11766	6	0	0
T2	13302	2	0	0
T3	14893	6	0	0
T4	6488	1	0	0
T5	8949	5	0	0
T6	12901	7	0	0
T7	12228	2	0	0
T8	12372	6	0	0
T9	24393	8	0	0
T10	27160	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	204	0	0
T3	446	1	0	0
T4	194	0	0	0
T5	268	0	0	0
T6	386	0	0	0
T7	365	0	0	0
T8	370	0	0	0
T9	734	0	0	0
T10	814	0	0	0
T11	2503	0	0	0
T12	299	0	0	0
T13	0	2	0	0
T37	0	3	0	0
T89	0	3	0	0
T92	0	1	0	0
T93	0	3	0	0
T97	0	3	0	0
T106	0	1	0	0
T110	0	13	0	0
T111	0	7	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	8830	0	0
T1	352	2	0	0
T2	397	2	0	0
T3	446	2	0	0
T4	194	1	0	0
T5	268	1	0	0
T6	386	1	0	0
T7	365	2	0	0
T8	370	2	0	0
T9	734	8	0	0
T10	814	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	21681	0	0
T1	2822	6	0	0
T2	3191	2	0	0
T3	3574	6	0	0
T4	1556	1	0	0
T5	2146	5	0	0
T6	3095	7	0	0
T7	2934	2	0	0
T8	2969	6	0	0
T9	5853	8	0	0
T10	6516	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	21681	0	0
T1	2822	6	0	0
T2	3191	2	0	0
T3	3574	6	0	0
T4	1556	1	0	0
T5	2146	5	0	0
T6	3095	7	0	0
T7	2934	2	0	0
T8	2969	6	0	0
T9	5853	8	0	0
T10	6516	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11043460	21681	0	0
T1	2730	6	0	0
T2	3005	2	0	0
T3	3427	6	0	0
T4	1538	1	0	0
T5	1794	5	0	0
T6	2637	7	0	0
T7	2819	2	0	0
T8	2679	6	0	0
T9	5310	8	0	0
T10	6499	1	0	0