Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T66
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T66
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T66,T67
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T66,T67
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12494304	13859	0	0
gen_assertions[0].RstEnOn_A	12494304	1197	0	0
gen_assertions[0].RstNOff_A	12494304	13859	0	0
gen_assertions[0].RstNOn_A	12494304	1197	0	0
gen_assertions[1].RstEnOff_A	49975938	12662	0	0
gen_assertions[1].RstEnOn_A	49975938	1157	0	0
gen_assertions[1].RstNOff_A	49975938	12662	0	0
gen_assertions[1].RstNOn_A	49975938	1157	0	0
gen_assertions[2].RstEnOff_A	24988638	12699	0	0
gen_assertions[2].RstEnOn_A	24988638	1158	0	0
gen_assertions[2].RstNOff_A	24988638	12699	0	0
gen_assertions[2].RstNOn_A	24988638	1158	0	0
gen_assertions[3].RstEnOff_A	24988630	12746	0	0
gen_assertions[3].RstEnOn_A	24988630	1188	0	0
gen_assertions[3].RstNOff_A	24988630	12746	0	0
gen_assertions[3].RstNOn_A	24988630	1188	0	0
gen_assertions[4].RstEnOff_A	1578096	21572	0	0
gen_assertions[4].RstEnOn_A	1578096	1269	0	0
gen_assertions[4].RstNOff_A	1578096	21572	0	0
gen_assertions[4].RstNOn_A	1578096	1269	0	0
gen_assertions[5].RstEnOff_A	12494304	14088	0	0
gen_assertions[5].RstEnOn_A	12494304	1282	0	0
gen_assertions[5].RstNOff_A	12494304	14088	0	0
gen_assertions[5].RstNOn_A	12494304	1282	0	0
gen_assertions[6].RstEnOff_A	12494304	14142	0	0
gen_assertions[6].RstEnOn_A	12494304	1339	0	0
gen_assertions[6].RstNOff_A	12494304	14142	0	0
gen_assertions[6].RstNOn_A	12494304	1339	0	0
gen_assertions[7].RstEnOff_A	12494304	14159	0	0
gen_assertions[7].RstEnOn_A	12494304	1356	0	0
gen_assertions[7].RstNOff_A	12494304	14159	0	0
gen_assertions[7].RstNOn_A	12494304	1356	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	13859	0	0
T1	2822	5	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	4	0	0
T9	5853	0	0	0
T10	6516	1	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1197	0	0
T1	2822	1	0	0
T2	3191	0	0	0
T3	3574	0	0	0
T4	1556	0	0	0
T5	2146	3	0	0
T6	3095	2	0	0
T7	2934	0	0	0
T8	2969	0	0	0
T9	5853	0	0	0
T10	6516	1	0	0
T22	0	2	0	0
T51	0	7	0	0
T55	0	1	0	0
T58	0	1	0	0
T66	0	2	0	0
T91	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	13859	0	0
T1	2822	5	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	4	0	0
T9	5853	0	0	0
T10	6516	1	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1197	0	0
T1	2822	1	0	0
T2	3191	0	0	0
T3	3574	0	0	0
T4	1556	0	0	0
T5	2146	3	0	0
T6	3095	2	0	0
T7	2934	0	0	0
T8	2969	0	0	0
T9	5853	0	0	0
T10	6516	1	0	0
T22	0	2	0	0
T51	0	7	0	0
T55	0	1	0	0
T58	0	1	0	0
T66	0	2	0	0
T91	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	12662	0	0
T1	11294	3	0	0
T2	12768	0	0	0
T3	14294	4	0	0
T4	6229	0	0	0
T5	8591	2	0	0
T6	12386	5	0	0
T7	11739	0	0	0
T8	11883	5	0	0
T9	23417	0	0	0
T10	26073	2	0	0
T11	0	23	0	0
T12	0	3	0	0
T13	0	29	0	0
T22	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	1157	0	0
T8	11883	1	0	0
T9	23417	0	0	0
T10	26073	2	0	0
T11	78637	0	0	0
T12	9616	0	0	0
T13	100826	0	0	0
T14	19314	0	0	0
T22	7100	1	0	0
T24	23256	0	0	0
T51	0	8	0	0
T55	0	1	0	0
T57	6690	0	0	0
T66	0	3	0	0
T67	0	1	0	0
T72	0	1	0	0
T86	0	6	0	0
T91	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	12662	0	0
T1	11294	3	0	0
T2	12768	0	0	0
T3	14294	4	0	0
T4	6229	0	0	0
T5	8591	2	0	0
T6	12386	5	0	0
T7	11739	0	0	0
T8	11883	5	0	0
T9	23417	0	0	0
T10	26073	2	0	0
T11	0	23	0	0
T12	0	3	0	0
T13	0	29	0	0
T22	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	1157	0	0
T8	11883	1	0	0
T9	23417	0	0	0
T10	26073	2	0	0
T11	78637	0	0	0
T12	9616	0	0	0
T13	100826	0	0	0
T14	19314	0	0	0
T22	7100	1	0	0
T24	23256	0	0	0
T51	0	8	0	0
T55	0	1	0	0
T57	6690	0	0	0
T66	0	3	0	0
T67	0	1	0	0
T72	0	1	0	0
T86	0	6	0	0
T91	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	12699	0	0
T1	5642	3	0	0
T2	6384	0	0	0
T3	7147	4	0	0
T4	3114	0	0	0
T5	4295	2	0	0
T6	6193	5	0	0
T7	5869	0	0	0
T8	5939	5	0	0
T9	11708	0	0	0
T10	13036	4	0	0
T11	0	23	0	0
T12	0	3	0	0
T13	0	29	0	0
T22	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	1158	0	0
T8	5939	1	0	0
T9	11708	0	0	0
T10	13036	4	0	0
T11	39314	0	0	0
T12	4807	0	0	0
T13	50423	0	0	0
T14	9656	0	0	0
T22	3549	0	0	0
T24	11621	0	0	0
T42	0	4	0	0
T51	0	10	0	0
T57	3345	0	0	0
T65	0	2	0	0
T66	0	5	0	0
T67	0	3	0	0
T86	0	7	0	0
T92	0	1	0	0
T93	0	29	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	12699	0	0
T1	5642	3	0	0
T2	6384	0	0	0
T3	7147	4	0	0
T4	3114	0	0	0
T5	4295	2	0	0
T6	6193	5	0	0
T7	5869	0	0	0
T8	5939	5	0	0
T9	11708	0	0	0
T10	13036	4	0	0
T11	0	23	0	0
T12	0	3	0	0
T13	0	29	0	0
T22	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	1158	0	0
T8	5939	1	0	0
T9	11708	0	0	0
T10	13036	4	0	0
T11	39314	0	0	0
T12	4807	0	0	0
T13	50423	0	0	0
T14	9656	0	0	0
T22	3549	0	0	0
T24	11621	0	0	0
T42	0	4	0	0
T51	0	10	0	0
T57	3345	0	0	0
T65	0	2	0	0
T66	0	5	0	0
T67	0	3	0	0
T86	0	7	0	0
T92	0	1	0	0
T93	0	29	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	12746	0	0
T1	5646	3	0	0
T2	6384	0	0	0
T3	7148	4	0	0
T4	3113	0	0	0
T5	4295	2	0	0
T6	6192	5	0	0
T7	5869	0	0	0
T8	5939	5	0	0
T9	11706	0	0	0
T10	13036	4	0	0
T11	0	23	0	0
T12	0	3	0	0
T13	0	29	0	0
T22	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	1188	0	0
T8	5939	1	0	0
T9	11706	0	0	0
T10	13036	4	0	0
T11	39322	0	0	0
T12	4809	0	0	0
T13	50415	0	0	0
T14	9657	0	0	0
T22	3549	0	0	0
T24	11621	0	0	0
T42	0	4	0	0
T51	0	9	0	0
T57	3344	0	0	0
T66	0	7	0	0
T67	0	3	0	0
T86	0	8	0	0
T93	0	29	0	0
T94	0	8	0	0
T95	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	12746	0	0
T1	5646	3	0	0
T2	6384	0	0	0
T3	7148	4	0	0
T4	3113	0	0	0
T5	4295	2	0	0
T6	6192	5	0	0
T7	5869	0	0	0
T8	5939	5	0	0
T9	11706	0	0	0
T10	13036	4	0	0
T11	0	23	0	0
T12	0	3	0	0
T13	0	29	0	0
T22	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	1188	0	0
T8	5939	1	0	0
T9	11706	0	0	0
T10	13036	4	0	0
T11	39322	0	0	0
T12	4809	0	0	0
T13	50415	0	0	0
T14	9657	0	0	0
T22	3549	0	0	0
T24	11621	0	0	0
T42	0	4	0	0
T51	0	9	0	0
T57	3344	0	0	0
T66	0	7	0	0
T67	0	3	0	0
T86	0	8	0	0
T93	0	29	0	0
T94	0	8	0	0
T95	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	21572	0	0
T1	352	7	0	0
T2	397	2	0	0
T3	446	6	0	0
T4	194	1	0	0
T5	268	4	0	0
T6	386	7	0	0
T7	365	2	0	0
T8	370	7	0	0
T9	734	3	0	0
T10	814	7	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	1269	0	0
T1	352	1	0	0
T2	397	0	0	0
T3	446	0	0	0
T4	194	0	0	0
T5	268	0	0	0
T6	386	0	0	0
T7	365	0	0	0
T8	370	1	0	0
T9	734	0	0	0
T10	814	6	0	0
T42	0	6	0	0
T51	0	11	0	0
T55	0	1	0	0
T66	0	7	0	0
T67	0	4	0	0
T86	0	9	0	0
T88	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	21572	0	0
T1	352	7	0	0
T2	397	2	0	0
T3	446	6	0	0
T4	194	1	0	0
T5	268	4	0	0
T6	386	7	0	0
T7	365	2	0	0
T8	370	7	0	0
T9	734	3	0	0
T10	814	7	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	1269	0	0
T1	352	1	0	0
T2	397	0	0	0
T3	446	0	0	0
T4	194	0	0	0
T5	268	0	0	0
T6	386	0	0	0
T7	365	0	0	0
T8	370	1	0	0
T9	734	0	0	0
T10	814	6	0	0
T42	0	6	0	0
T51	0	11	0	0
T55	0	1	0	0
T66	0	7	0	0
T67	0	4	0	0
T86	0	9	0	0
T88	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	14088	0	0
T1	2822	4	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	4	0	0
T9	5853	0	0	0
T10	6516	7	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1282	0	0
T10	6516	7	0	0
T11	19658	0	0	0
T12	2402	0	0	0
T13	25205	0	0	0
T14	4827	0	0	0
T22	1774	0	0	0
T23	3464	0	0	0
T24	5811	0	0	0
T42	0	7	0	0
T51	0	11	0	0
T57	1671	0	0	0
T66	9009	9	0	0
T67	0	6	0	0
T86	0	9	0	0
T92	0	1	0	0
T93	0	36	0	0
T94	0	10	0	0
T95	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	14088	0	0
T1	2822	4	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	4	0	0
T9	5853	0	0	0
T10	6516	7	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1282	0	0
T10	6516	7	0	0
T11	19658	0	0	0
T12	2402	0	0	0
T13	25205	0	0	0
T14	4827	0	0	0
T22	1774	0	0	0
T23	3464	0	0	0
T24	5811	0	0	0
T42	0	7	0	0
T51	0	11	0	0
T57	1671	0	0	0
T66	9009	9	0	0
T67	0	6	0	0
T86	0	9	0	0
T92	0	1	0	0
T93	0	36	0	0
T94	0	10	0	0
T95	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	14142	0	0
T1	2822	4	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	4	0	0
T9	5853	0	0	0
T10	6516	9	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1339	0	0
T10	6516	9	0	0
T11	19658	0	0	0
T12	2402	0	0	0
T13	25205	0	0	0
T14	4827	0	0	0
T22	1774	0	0	0
T23	3464	0	0	0
T24	5811	0	0	0
T42	0	6	0	0
T51	0	12	0	0
T57	1671	0	0	0
T66	9009	9	0	0
T67	0	6	0	0
T86	0	11	0	0
T93	0	29	0	0
T94	0	13	0	0
T96	0	9	0	0
T97	0	29	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	14142	0	0
T1	2822	4	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	4	0	0
T9	5853	0	0	0
T10	6516	9	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1339	0	0
T10	6516	9	0	0
T11	19658	0	0	0
T12	2402	0	0	0
T13	25205	0	0	0
T14	4827	0	0	0
T22	1774	0	0	0
T23	3464	0	0	0
T24	5811	0	0	0
T42	0	6	0	0
T51	0	12	0	0
T57	1671	0	0	0
T66	9009	9	0	0
T67	0	6	0	0
T86	0	11	0	0
T93	0	29	0	0
T94	0	13	0	0
T96	0	9	0	0
T97	0	29	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	14159	0	0
T1	2822	5	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	5	0	0
T9	5853	0	0	0
T10	6516	9	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1356	0	0
T1	2822	1	0	0
T2	3191	0	0	0
T3	3574	0	0	0
T4	1556	0	0	0
T5	2146	0	0	0
T6	3095	0	0	0
T7	2934	0	0	0
T8	2969	1	0	0
T9	5853	0	0	0
T10	6516	9	0	0
T42	0	9	0	0
T51	0	13	0	0
T66	0	11	0	0
T67	0	7	0	0
T86	0	10	0	0
T93	0	28	0	0
T94	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	14159	0	0
T1	2822	5	0	0
T2	3191	0	0	0
T3	3574	4	0	0
T4	1556	0	0	0
T5	2146	4	0	0
T6	3095	6	0	0
T7	2934	0	0	0
T8	2969	5	0	0
T9	5853	0	0	0
T10	6516	9	0	0
T11	0	26	0	0
T12	0	4	0	0
T13	0	33	0	0
T22	0	3	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	1356	0	0
T1	2822	1	0	0
T2	3191	0	0	0
T3	3574	0	0	0
T4	1556	0	0	0
T5	2146	0	0	0
T6	3095	0	0	0
T7	2934	0	0	0
T8	2969	1	0	0
T9	5853	0	0	0
T10	6516	9	0	0
T42	0	9	0	0
T51	0	13	0	0
T66	0	11	0	0
T67	0	7	0	0
T86	0	10	0	0
T93	0	28	0	0
T94	0	12	0	0