Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	843425740	437689869	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	843425740	437689869	0	0
T1	190552	120002	0	0
T2	215454	52642	0	0
T3	241238	167454	0	0
T4	105088	61283	0	0
T5	144950	80655	0	0
T6	208984	140998	0	0
T7	198076	50246	0	0
T8	200446	120076	0	0
T9	395148	42977	0	0
T10	439956	390782	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	52059582	30446557	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	30446557	0	0
T1	11766	7811	0	0
T2	13302	3638	0	0
T3	14893	10919	0	0
T4	6488	3823	0	0
T5	8949	6284	0	0
T6	12901	10200	0	0
T7	12228	3456	0	0
T8	12372	8179	0	0
T9	24393	2990	0	0
T10	27160	24484	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	49975938	29227396	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	29227396	0	0
T1	11294	7497	0	0
T2	12768	3492	0	0
T3	14294	10480	0	0
T4	6229	3670	0	0
T5	8591	6032	0	0
T6	12386	9792	0	0
T7	11739	3318	0	0
T8	11883	7856	0	0
T9	23417	2870	0	0
T10	26073	23504	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988638	14609941	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	14609941	0	0
T1	5642	3743	0	0
T2	6384	1746	0	0
T3	7147	5239	0	0
T4	3114	1835	0	0
T5	4295	3015	0	0
T6	6193	4896	0	0
T7	5869	1658	0	0
T8	5939	3927	0	0
T9	11708	1429	0	0
T10	13036	11752	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	7301771	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	7301771	0	0
T1	2822	1873	0	0
T2	3191	872	0	0
T3	3574	2621	0	0
T4	1556	917	0	0
T5	2146	1507	0	0
T6	3095	2447	0	0
T7	2934	829	0	0
T8	2969	1963	0	0
T9	5853	710	0	0
T10	6516	5875	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988630	14609799	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	14609799	0	0
T1	5646	3746	0	0
T2	6384	1746	0	0
T3	7148	5240	0	0
T4	3113	1835	0	0
T5	4295	3015	0	0
T6	6192	4896	0	0
T7	5869	1658	0	0
T8	5939	3927	0	0
T9	11706	1429	0	0
T10	13036	11752	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	52059582	26829462	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	26829462	0	0
T1	11766	7435	0	0
T2	13302	3627	0	0
T3	14893	10317	0	0
T4	6488	3817	0	0
T5	8949	4733	0	0
T6	12901	8434	0	0
T7	12228	3443	0	0
T8	12372	7364	0	0
T9	24393	2891	0	0
T10	27160	24478	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	52059582	26109086	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	26109086	0	0
T1	11766	7270	0	0
T2	13302	2893	0	0
T3	14893	10149	0	0
T4	6488	3750	0	0
T5	8949	4632	0	0
T6	12901	8317	0	0
T7	12228	2778	0	0
T8	12372	7197	0	0
T9	24393	2398	0	0
T10	27160	24412	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	52059582	26829389	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	26829389	0	0
T1	11766	7435	0	0
T2	13302	3627	0	0
T3	14893	10317	0	0
T4	6488	3817	0	0
T5	8949	4733	0	0
T6	12901	8434	0	0
T7	12228	3443	0	0
T8	12372	7364	0	0
T9	24393	2891	0	0
T10	27160	24478	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	52059582	26110719	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	26110719	0	0
T1	11766	7270	0	0
T2	13302	2893	0	0
T3	14893	10149	0	0
T4	6488	3750	0	0
T5	8949	4632	0	0
T6	12901	8317	0	0
T7	12228	2778	0	0
T8	12372	7197	0	0
T9	24393	2398	0	0
T10	27160	24412	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1578096	795425	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	795425	0	0
T1	352	216	0	0
T2	397	107	0	0
T3	446	303	0	0
T4	194	113	0	0
T5	268	137	0	0
T6	386	246	0	0
T7	365	101	0	0
T8	370	213	0	0
T9	734	77	0	0
T10	814	733	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	49975938	25756828	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	25756828	0	0
T1	11294	7136	0	0
T2	12768	3481	0	0
T3	14294	9902	0	0
T4	6229	3664	0	0
T5	8591	4541	0	0
T6	12386	8096	0	0
T7	11739	3306	0	0
T8	11883	7074	0	0
T9	23417	2815	0	0
T10	26073	23499	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	49975938	25063498	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	25063498	0	0
T1	11294	6976	0	0
T2	12768	2777	0	0
T3	14294	9742	0	0
T4	6229	3600	0	0
T5	8591	4445	0	0
T6	12386	7984	0	0
T7	11739	2666	0	0
T8	11883	6914	0	0
T9	23417	2303	0	0
T10	26073	23435	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988638	12868222	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	12868222	0	0
T1	5642	3561	0	0
T2	6384	1740	0	0
T3	7147	4949	0	0
T4	3114	1832	0	0
T5	4295	2268	0	0
T6	6193	4045	0	0
T7	5869	1652	0	0
T8	5939	3533	0	0
T9	11708	1405	0	0
T10	13036	11749	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988638	12521648	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	12521648	0	0
T1	5642	3481	0	0
T2	6384	1388	0	0
T3	7147	4869	0	0
T4	3114	1800	0	0
T5	4295	2220	0	0
T6	6193	3989	0	0
T7	5869	1332	0	0
T8	5939	3453	0	0
T9	11708	1149	0	0
T10	13036	11717	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6407002	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6407002	0	0
T1	2822	1774	0	0
T2	3191	868	0	0
T3	3574	2468	0	0
T4	1556	915	0	0
T5	2146	1127	0	0
T6	3095	2012	0	0
T7	2934	825	0	0
T8	2969	1759	0	0
T9	5853	684	0	0
T10	6516	5873	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6233685	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6233685	0	0
T1	2822	1734	0	0
T2	3191	692	0	0
T3	3574	2428	0	0
T4	1556	899	0	0
T5	2146	1103	0	0
T6	3095	1984	0	0
T7	2934	665	0	0
T8	2969	1719	0	0
T9	5853	556	0	0
T10	6516	5857	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6407002	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6407002	0	0
T1	2822	1774	0	0
T2	3191	868	0	0
T3	3574	2468	0	0
T4	1556	915	0	0
T5	2146	1127	0	0
T6	3095	2012	0	0
T7	2934	825	0	0
T8	2969	1759	0	0
T9	5853	684	0	0
T10	6516	5873	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6233685	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6233685	0	0
T1	2822	1734	0	0
T2	3191	692	0	0
T3	3574	2428	0	0
T4	1556	899	0	0
T5	2146	1103	0	0
T6	3095	1984	0	0
T7	2934	665	0	0
T8	2969	1719	0	0
T9	5853	556	0	0
T10	6516	5857	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988630	12868160	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	12868160	0	0
T1	5646	3564	0	0
T2	6384	1740	0	0
T3	7148	4950	0	0
T4	3113	1832	0	0
T5	4295	2268	0	0
T6	6192	4045	0	0
T7	5869	1652	0	0
T8	5939	3533	0	0
T9	11706	1405	0	0
T10	13036	11749	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988630	12521486	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	12521486	0	0
T1	5646	3484	0	0
T2	6384	1388	0	0
T3	7148	4870	0	0
T4	3113	1800	0	0
T5	4295	2220	0	0
T6	6192	3989	0	0
T7	5869	1332	0	0
T8	5939	3453	0	0
T9	11706	1149	0	0
T10	13036	11717	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	52059582	25813781	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52059582	25813781	0	0
T1	11766	7224	0	0
T2	13302	2893	0	0
T3	14893	10055	0	0
T4	6488	3750	0	0
T5	8949	4603	0	0
T6	12901	8159	0	0
T7	12228	2778	0	0
T8	12372	7090	0	0
T9	24393	2398	0	0
T10	27160	24412	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6336269	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6336269	0	0
T1	2822	1763	0	0
T2	3191	868	0	0
T3	3574	2445	0	0
T4	1556	915	0	0
T5	2146	1120	0	0
T6	3095	1974	0	0
T7	2934	825	0	0
T8	2969	1733	0	0
T9	5853	694	0	0
T10	6516	5873	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6078375	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6078375	0	0
T1	2822	1702	0	0
T2	3191	692	0	0
T3	3574	2428	0	0
T4	1556	899	0	0
T5	2146	1086	0	0
T6	3095	1976	0	0
T7	2934	665	0	0
T8	2969	1719	0	0
T9	5853	566	0	0
T10	6516	5743	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	49975938	24438479	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49975938	24438479	0	0
T1	11294	6976	0	0
T2	12768	2777	0	0
T3	14294	9742	0	0
T4	6229	3600	0	0
T5	8591	4445	0	0
T6	12386	7984	0	0
T7	11739	2666	0	0
T8	11883	6795	0	0
T9	23417	2303	0	0
T10	26073	22086	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988638	12203747	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988638	12203747	0	0
T1	5642	3481	0	0
T2	6384	1388	0	0
T3	7147	4869	0	0
T4	3114	1800	0	0
T5	4295	2220	0	0
T6	6193	3989	0	0
T7	5869	1332	0	0
T8	5939	3398	0	0
T9	11708	1149	0	0
T10	13036	10910	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	24988630	12214801	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24988630	12214801	0	0
T1	5646	3484	0	0
T2	6384	1388	0	0
T3	7148	4870	0	0
T4	3113	1800	0	0
T5	4295	2220	0	0
T6	6192	3989	0	0
T7	5869	1332	0	0
T8	5939	3402	0	0
T9	11706	1149	0	0
T10	13036	10730	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1578096	754021	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	754021	0	0
T1	352	208	0	0
T2	397	85	0	0
T3	446	299	0	0
T4	194	111	0	0
T5	268	134	0	0
T6	386	244	0	0
T7	365	81	0	0
T8	370	206	0	0
T9	734	61	0	0
T10	814	641	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6079525	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6079525	0	0
T1	2822	1734	0	0
T2	3191	692	0	0
T3	3574	2428	0	0
T4	1556	899	0	0
T5	2146	1103	0	0
T6	3095	1984	0	0
T7	2934	665	0	0
T8	2969	1719	0	0
T9	5853	566	0	0
T10	6516	5302	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6084390	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6084390	0	0
T1	2822	1734	0	0
T2	3191	692	0	0
T3	3574	2428	0	0
T4	1556	899	0	0
T5	2146	1103	0	0
T6	3095	1984	0	0
T7	2934	665	0	0
T8	2969	1719	0	0
T9	5853	566	0	0
T10	6516	5141	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12494304	6089344	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12494304	6089344	0	0
T1	2822	1716	0	0
T2	3191	692	0	0
T3	3574	2428	0	0
T4	1556	899	0	0
T5	2146	1103	0	0
T6	3095	1984	0	0
T7	2934	665	0	0
T8	2969	1702	0	0
T9	5853	566	0	0
T10	6516	5270	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1578096	932414	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	932414	0	0
T1	352	235	0	0
T2	397	111	0	0
T3	446	329	0	0
T4	194	115	0	0
T5	268	189	0	0
T6	386	307	0	0
T7	365	105	0	0
T8	370	247	0	0
T9	734	93	0	0
T10	814	735	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1578096	913962	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578096	913962	0	0
T1	352	231	0	0
T2	397	89	0	0
T3	446	325	0	0
T4	194	113	0	0
T5	268	187	0	0
T6	386	305	0	0
T7	365	85	0	0
T8	370	243	0	0
T9	734	77	0	0
T10	814	733	0	0