Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11838790	8531	0	0
alert_regwen_rd_A	11838790	3402	0	0
cpu_regwen_rd_A	11838790	3414	0	0
sw_rst_ctrl_n_0_rd_A	11838790	7979	0	0
sw_rst_ctrl_n_1_rd_A	11838790	7495	0	0
sw_rst_ctrl_n_2_rd_A	11838790	7616	0	0
sw_rst_ctrl_n_3_rd_A	11838790	8214	0	0
sw_rst_ctrl_n_4_rd_A	11838790	7616	0	0
sw_rst_ctrl_n_5_rd_A	11838790	7959	0	0
sw_rst_ctrl_n_6_rd_A	11838790	7677	0	0
sw_rst_ctrl_n_7_rd_A	11838790	7854	0	0
sw_rst_regwen_0_rd_A	11838790	4077	0	0
sw_rst_regwen_1_rd_A	11838790	3864	0	0
sw_rst_regwen_2_rd_A	11838790	3968	0	0
sw_rst_regwen_3_rd_A	11838790	3959	0	0
sw_rst_regwen_4_rd_A	11838790	4110	0	0
sw_rst_regwen_5_rd_A	11838790	3955	0	0
sw_rst_regwen_6_rd_A	11838790	3802	0	0
sw_rst_regwen_7_rd_A	11838790	4040	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	8531	0	0
T76	3384	230	0	0
T77	18622	1	0	0
T78	2807	8	0	0
T79	5556	100	0	0
T80	18154	2	0	0
T98	4313	298	0	0
T99	4025	422	0	0
T100	2668	43	0	0
T104	17261	2	0	0
T126	12587	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3402	0	0
T43	42085	0	0	0
T44	42415	0	0	0
T50	5269	0	0	0
T51	11814	0	0	0
T52	25849	0	0	0
T53	1489	0	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T89	0	63	0	0
T90	32469	27	0	0
T91	2330	0	0	0
T106	0	57	0	0
T112	0	197	0	0
T115	0	105	0	0
T133	0	60	0	0
T134	0	25	0	0
T135	0	88	0	0
T136	0	346	0	0
T137	0	75	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3414	0	0
T43	42085	0	0	0
T44	42415	0	0	0
T50	5269	0	0	0
T51	11814	0	0	0
T52	25849	0	0	0
T53	1489	0	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T89	0	83	0	0
T90	32469	30	0	0
T91	2330	0	0	0
T106	0	45	0	0
T112	0	225	0	0
T115	0	128	0	0
T133	0	53	0	0
T134	0	17	0	0
T135	0	75	0	0
T136	0	363	0	0
T137	0	63	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7979	0	0
T6	2637	6	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	158	0	0
T51	0	219	0	0
T55	0	22	0	0
T57	1629	0	0	0
T66	0	104	0	0
T67	0	146	0	0
T86	0	100	0	0
T89	0	70	0	0
T90	0	55	0	0
T106	0	37	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7495	0	0
T6	2637	17	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	123	0	0
T51	0	167	0	0
T55	0	17	0	0
T57	1629	0	0	0
T66	0	82	0	0
T67	0	112	0	0
T86	0	85	0	0
T89	0	71	0	0
T90	0	22	0	0
T106	0	47	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7616	0	0
T6	2637	12	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	136	0	0
T51	0	181	0	0
T55	0	11	0	0
T57	1629	0	0	0
T66	0	77	0	0
T67	0	96	0	0
T86	0	68	0	0
T89	0	78	0	0
T90	0	17	0	0
T106	0	25	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	8214	0	0
T6	2637	18	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	130	0	0
T51	0	176	0	0
T55	0	16	0	0
T57	1629	0	0	0
T66	0	141	0	0
T67	0	88	0	0
T86	0	105	0	0
T89	0	72	0	0
T90	0	19	0	0
T106	0	49	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7616	0	0
T6	2637	6	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	141	0	0
T51	0	200	0	0
T55	0	15	0	0
T57	1629	0	0	0
T66	0	74	0	0
T67	0	100	0	0
T86	0	87	0	0
T89	0	76	0	0
T90	0	22	0	0
T106	0	41	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7959	0	0
T6	2637	13	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	126	0	0
T51	0	199	0	0
T55	0	18	0	0
T57	1629	0	0	0
T66	0	119	0	0
T67	0	129	0	0
T86	0	95	0	0
T89	0	73	0	0
T90	0	52	0	0
T106	0	53	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7677	0	0
T6	2637	8	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	136	0	0
T51	0	202	0	0
T55	0	12	0	0
T57	1629	0	0	0
T66	0	96	0	0
T67	0	127	0	0
T86	0	77	0	0
T89	0	59	0	0
T90	0	17	0	0
T106	0	34	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	7854	0	0
T6	2637	16	0	0
T7	2819	0	0	0
T8	2679	0	0	0
T9	5310	0	0	0
T10	6499	0	0	0
T11	15814	0	0	0
T12	2162	0	0	0
T13	20031	0	0	0
T24	5459	0	0	0
T42	0	120	0	0
T51	0	167	0	0
T55	0	14	0	0
T57	1629	0	0	0
T66	0	72	0	0
T67	0	115	0	0
T86	0	89	0	0
T89	0	89	0	0
T90	0	29	0	0
T106	0	29	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	4077	0	0
T15	2299	0	0	0
T42	0	30	0	0
T51	0	19	0	0
T55	0	5	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	20	0	0
T67	8481	38	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	29	0	0
T89	0	68	0	0
T90	32469	40	0	0
T91	2330	0	0	0
T106	0	51	0	0
T138	0	46	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3864	0	0
T15	2299	0	0	0
T42	0	32	0	0
T51	0	13	0	0
T55	0	14	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	24	0	0
T67	8481	37	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	24	0	0
T89	0	80	0	0
T90	32469	28	0	0
T91	2330	0	0	0
T106	0	31	0	0
T138	0	21	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3968	0	0
T15	2299	0	0	0
T42	0	37	0	0
T51	0	45	0	0
T55	0	9	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	19	0	0
T67	8481	23	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	6	0	0
T89	0	92	0	0
T90	32469	48	0	0
T91	2330	0	0	0
T106	0	65	0	0
T138	0	32	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3959	0	0
T15	2299	0	0	0
T42	0	25	0	0
T51	0	39	0	0
T55	0	3	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	11	0	0
T67	8481	38	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	10	0	0
T89	0	62	0	0
T90	32469	31	0	0
T91	2330	0	0	0
T106	0	21	0	0
T138	0	30	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	4110	0	0
T15	2299	0	0	0
T42	0	42	0	0
T51	0	46	0	0
T55	0	7	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	15	0	0
T67	8481	24	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	16	0	0
T89	0	99	0	0
T90	32469	49	0	0
T91	2330	0	0	0
T106	0	42	0	0
T138	0	34	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3955	0	0
T15	2299	0	0	0
T42	0	27	0	0
T51	0	35	0	0
T55	0	12	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	19	0	0
T67	8481	33	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	22	0	0
T89	0	71	0	0
T90	32469	6	0	0
T91	2330	0	0	0
T106	0	40	0	0
T138	0	24	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	3802	0	0
T15	2299	0	0	0
T42	0	37	0	0
T51	0	26	0	0
T55	0	10	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	22	0	0
T67	8481	40	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	6	0	0
T89	0	70	0	0
T90	32469	17	0	0
T91	2330	0	0	0
T106	0	72	0	0
T138	0	19	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11838790	4040	0	0
T15	2299	0	0	0
T42	0	33	0	0
T51	0	35	0	0
T55	0	12	0	0
T58	2593	0	0	0
T59	3282	0	0	0
T66	8966	11	0	0
T67	8481	35	0	0
T72	4310	0	0	0
T73	5411	0	0	0
T81	1659	0	0	0
T86	0	6	0	0
T89	0	63	0	0
T90	32469	20	0	0
T91	2330	0	0	0
T106	0	69	0	0
T138	0	41	0	0