RSTMGR Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.560s 250.499us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.420s 154.664us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.310s 76.487us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 5.120s 487.069us 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.110s 155.660us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.360s 188.743us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.310s 76.487us 20 20 100.00
rstmgr_csr_aliasing 2.110s 155.660us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.570s 175.828us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 4.180s 493.283us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.050s 252.151us 50 50 100.00
V2 reset_info rstmgr_reset 12.510s 2.046ms 50 50 100.00
V2 cpu_info rstmgr_reset 12.510s 2.046ms 50 50 100.00
V2 alert_info rstmgr_reset 12.510s 2.046ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 12.510s 2.046ms 50 50 100.00
V2 stress_all rstmgr_stress_all 39.320s 7.063ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.350s 87.356us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.440s 611.239us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.440s 611.239us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.420s 154.664us 5 5 100.00
rstmgr_csr_rw 1.310s 76.487us 20 20 100.00
rstmgr_csr_aliasing 2.110s 155.660us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 216.623us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.420s 154.664us 5 5 100.00
rstmgr_csr_rw 1.310s 76.487us 20 20 100.00
rstmgr_csr_aliasing 2.110s 155.660us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 216.623us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 41.690s 17.575ms 5 5 100.00
rstmgr_tl_intg_err 4.100s 803.241us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 41.690s 17.575ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 41.690s 17.575ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 4.100s 803.241us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 2.000s 168.997us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 13.900s 2.359ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 2.000s 244.695us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 41.690s 17.575ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.310s 76.487us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.310s 76.487us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Past Results