Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605552	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

362735

1

T2

126

T3

76

T5

111

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515896	1			T1	1		T2	186		T3	99
values[0x0]	225802	1			T2	92		T3	57		T5	77
values[0x1]	226589	1			T2	101		T3	56		T5	80

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	508023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460264

1

T1

1

T2

163

T3

95

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4268	1			T8	1		T9	1		T11	2
valid_sources[0x01]	3739	1			T8	2		T9	4		T11	2
valid_sources[0x02]	3212	1			T8	4		T14	3		T23	12
valid_sources[0x03]	3793	1			T8	4		T9	1		T23	2
valid_sources[0x04]	4262	1			T8	2		T11	1		T54	1
valid_sources[0x05]	2808	1			T8	1		T9	2		T11	1
valid_sources[0x06]	2741	1			T8	7		T9	5		T11	1
valid_sources[0x07]	4040	1			T8	4		T9	3		T23	8
valid_sources[0x08]	3358	1			T6	2		T8	5		T9	3
valid_sources[0x09]	3900	1			T8	5		T9	1		T11	3
valid_sources[0x0a]	3697	1			T8	3		T9	4		T23	3
valid_sources[0x0b]	4029	1			T8	2		T9	1		T23	3
valid_sources[0x0c]	3620	1			T8	3		T9	1		T11	1
valid_sources[0x0d]	3003	1			T8	5		T9	4		T54	3
valid_sources[0x0e]	3713	1			T8	8		T9	1		T11	1
valid_sources[0x0f]	3631	1			T8	1		T11	1		T14	6
valid_sources[0x10]	7000	1			T9	1		T11	3		T23	20
valid_sources[0x11]	4061	1			T8	3		T9	3		T11	1
valid_sources[0x12]	3291	1			T8	5		T9	1		T23	15
valid_sources[0x13]	3268	1			T8	2		T9	1		T14	4
valid_sources[0x14]	3234	1			T6	1		T8	4		T9	1
valid_sources[0x15]	3171	1			T8	6		T9	2		T14	2
valid_sources[0x16]	3858	1			T8	3		T9	1		T23	1
valid_sources[0x17]	3962	1			T8	2		T23	8		T25	1
valid_sources[0x18]	3242	1			T8	4		T14	5		T23	5
valid_sources[0x19]	3904	1			T8	1		T9	2		T14	3
valid_sources[0x1a]	3286	1			T8	3		T9	1		T14	5
valid_sources[0x1b]	3893	1			T8	3		T9	2		T23	9
valid_sources[0x1c]	3252	1			T8	7		T23	2		T25	1
valid_sources[0x1d]	2806	1			T8	7		T9	1		T14	7
valid_sources[0x1e]	3464	1			T8	5		T9	2		T14	12
valid_sources[0x1f]	4009	1			T8	1		T23	6		T50	1
valid_sources[0x20]	3947	1			T8	8		T9	1		T50	11
valid_sources[0x21]	3147	1			T8	6		T9	2		T14	3
valid_sources[0x22]	3502	1			T8	4		T11	2		T23	18
valid_sources[0x23]	3902	1			T8	3		T9	1		T23	3
valid_sources[0x24]	3285	1			T8	5		T9	1		T23	6
valid_sources[0x25]	3708	1			T8	3		T9	1		T23	10
valid_sources[0x26]	3707	1			T8	5		T14	4		T23	14
valid_sources[0x27]	3315	1			T8	2		T9	3		T23	42
valid_sources[0x28]	3531	1			T8	7		T9	3		T11	1
valid_sources[0x29]	4639	1			T8	2		T9	2		T11	2
valid_sources[0x2a]	3343	1			T8	3		T9	2		T23	2
valid_sources[0x2b]	3926	1			T8	3		T11	5		T23	4
valid_sources[0x2c]	3177	1			T8	5		T11	2		T14	5
valid_sources[0x2d]	3026	1			T8	7		T23	5		T25	3
valid_sources[0x2e]	3052	1			T23	10		T24	1		T50	6
valid_sources[0x2f]	4006	1			T8	1		T9	4		T14	2
valid_sources[0x30]	6509	1			T8	5		T9	3		T11	1
valid_sources[0x31]	4233	1			T8	4		T23	8		T25	1
valid_sources[0x32]	3636	1			T8	2		T9	2		T11	2
valid_sources[0x33]	3238	1			T9	1		T11	1		T14	2
valid_sources[0x34]	3408	1			T7	1		T8	4		T9	1
valid_sources[0x35]	3034	1			T8	2		T23	10		T24	1
valid_sources[0x36]	3736	1			T8	3		T23	3		T25	1
valid_sources[0x37]	3475	1			T8	3		T9	3		T11	2
valid_sources[0x38]	6793	1			T8	2		T23	7		T24	2
valid_sources[0x39]	4122	1			T8	4		T9	1		T11	2
valid_sources[0x3a]	2893	1			T8	5		T11	2		T14	3
valid_sources[0x3b]	6633	1			T8	7		T23	1		T24	1
valid_sources[0x3c]	3838	1			T8	5		T9	2		T23	4
valid_sources[0x3d]	3706	1			T8	2		T9	2		T11	1
valid_sources[0x3e]	4529	1			T8	3		T23	14		T24	1
valid_sources[0x3f]	3644	1			T8	7		T11	1		T23	14
valid_sources[0x40]	3606	1			T8	3		T9	2		T11	2
valid_sources[0x41]	3758	1			T8	2		T9	5		T23	6
valid_sources[0x42]	3379	1			T8	2		T9	3		T11	1
valid_sources[0x43]	4438	1			T8	4		T14	14		T23	11
valid_sources[0x44]	7665	1			T8	1		T9	3		T11	1
valid_sources[0x45]	3191	1			T8	3		T9	1		T11	1
valid_sources[0x46]	3469	1			T8	3		T9	1		T11	2
valid_sources[0x47]	3257	1			T8	2		T9	1		T23	3
valid_sources[0x48]	3657	1			T8	1		T9	3		T23	9
valid_sources[0x49]	3914	1			T8	9		T11	1		T12	712
valid_sources[0x4a]	4202	1			T8	1		T9	1		T54	1
valid_sources[0x4b]	7231	1			T8	5		T14	3		T23	18
valid_sources[0x4c]	6472	1			T8	4		T9	3		T23	9
valid_sources[0x4d]	3392	1			T8	5		T9	1		T11	1
valid_sources[0x4e]	2866	1			T8	1		T9	1		T11	1
valid_sources[0x4f]	3010	1			T8	3		T9	5		T54	1
valid_sources[0x50]	4357	1			T8	1		T9	1		T14	3
valid_sources[0x51]	3240	1			T8	1		T23	20		T25	3
valid_sources[0x52]	3282	1			T8	7		T9	1		T11	1
valid_sources[0x53]	4146	1			T8	4		T9	2		T11	2
valid_sources[0x54]	3566	1			T8	7		T9	3		T11	1
valid_sources[0x55]	3930	1			T8	2		T9	2		T23	9
valid_sources[0x56]	4306	1			T8	3		T11	1		T14	3
valid_sources[0x57]	3682	1			T8	1		T9	4		T14	2
valid_sources[0x58]	2931	1			T8	2		T9	2		T11	1
valid_sources[0x59]	3495	1			T8	5		T9	1		T11	1
valid_sources[0x5a]	2819	1			T9	1		T23	3		T50	6
valid_sources[0x5b]	5011	1			T8	3		T23	8		T24	2
valid_sources[0x5c]	4498	1			T8	4		T9	4		T10	212
valid_sources[0x5d]	3457	1			T8	3		T9	4		T23	6
valid_sources[0x5e]	4408	1			T8	4		T9	3		T24	1
valid_sources[0x5f]	3691	1			T2	379		T8	2		T9	2
valid_sources[0x60]	4951	1			T8	1		T23	27		T49	155
valid_sources[0x61]	4009	1			T8	3		T11	2		T23	9
valid_sources[0x62]	3353	1			T8	3		T23	15		T25	2
valid_sources[0x63]	3417	1			T8	4		T9	1		T11	1
valid_sources[0x64]	3395	1			T8	3		T9	2		T11	2
valid_sources[0x65]	3155	1			T8	1		T9	1		T14	3
valid_sources[0x66]	3455	1			T8	3		T23	5		T50	4
valid_sources[0x67]	2850	1			T8	1		T9	3		T11	1
valid_sources[0x68]	6541	1			T8	4		T14	5		T23	7
valid_sources[0x69]	4242	1			T8	5		T9	4		T14	2
valid_sources[0x6a]	3619	1			T8	3		T9	1		T11	1
valid_sources[0x6b]	3321	1			T8	2		T9	3		T11	1
valid_sources[0x6c]	3940	1			T6	1		T8	1		T14	5
valid_sources[0x6d]	4465	1			T8	4		T11	1		T14	8
valid_sources[0x6e]	3100	1			T8	5		T9	5		T23	2
valid_sources[0x6f]	2986	1			T8	6		T9	1		T11	2
valid_sources[0x70]	4286	1			T8	1		T9	1		T11	1
valid_sources[0x71]	3897	1			T8	2		T9	1		T11	2
valid_sources[0x72]	3161	1			T8	4		T9	1		T11	1
valid_sources[0x73]	3625	1			T8	5		T9	1		T23	4
valid_sources[0x74]	3852	1			T1	1		T9	2		T23	2
valid_sources[0x75]	3222	1			T9	1		T11	1		T23	1
valid_sources[0x76]	3772	1			T8	4		T9	1		T23	7
valid_sources[0x77]	3377	1			T8	2		T9	3		T23	19
valid_sources[0x78]	3137	1			T8	4		T9	3		T23	15
valid_sources[0x79]	6542	1			T8	1		T9	4		T11	1
valid_sources[0x7a]	3328	1			T8	3		T9	1		T14	2
valid_sources[0x7b]	3239	1			T8	3		T9	1		T23	8
valid_sources[0x7c]	4154	1			T8	2		T9	2		T14	1
valid_sources[0x7d]	3541	1			T6	2		T8	3		T9	1
valid_sources[0x7e]	3621	1			T8	2		T9	1		T11	1
valid_sources[0x7f]	2761	1			T8	1		T11	2		T23	3
valid_sources[0x80]	3510	1			T8	3		T9	4		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241698

1

T2

76

T3

47

T5

81

values[0x0]

all_enables

biggest_size

79004

1

T2

34

T3

20

T5

20

values[0x1]

all_enables

biggest_size

42033

1

T2

16

T3

9

T5

10