Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11229616	13081	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11229616	120881	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11229616	6546749	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11229616	192324	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11229616	13081	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11229616	120881	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11229616	6546749	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11229616	192324	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	13081	0	0
T2	2367	4	0	0
T3	3417	4	0	0
T4	6542	0	0	0
T5	5203	17	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	0	0	0
T9	2486	4	0	0
T10	3077	4	0	0
T11	3364	9	0	0
T14	0	4	0	0
T23	0	35	0	0
T24	0	12	0	0
T25	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	120881	0	0
T2	2367	37	0	0
T3	3417	37	0	0
T4	6542	0	0	0
T5	5203	153	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	0	0	0
T9	2486	37	0	0
T10	3077	37	0	0
T11	3364	81	0	0
T14	0	38	0	0
T23	0	317	0	0
T24	0	108	0	0
T25	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	6546749	0	0
T1	5152	931	0	0
T2	2367	1424	0	0
T3	3417	2473	0	0
T4	6542	661	0	0
T5	5203	4371	0	0
T6	1806	1187	0	0
T7	3815	891	0	0
T8	10782	10164	0	0
T9	2486	1483	0	0
T10	3077	2135	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	192324	0	0
T2	2367	44	0	0
T3	3417	62	0	0
T4	6542	0	0	0
T5	5203	235	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	0	0	0
T9	2486	65	0	0
T10	3077	67	0	0
T11	3364	143	0	0
T14	0	43	0	0
T23	0	521	0	0
T24	0	171	0	0
T25	0	65	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	13081	0	0
T2	2367	4	0	0
T3	3417	4	0	0
T4	6542	0	0	0
T5	5203	17	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	0	0	0
T9	2486	4	0	0
T10	3077	4	0	0
T11	3364	9	0	0
T14	0	4	0	0
T23	0	35	0	0
T24	0	12	0	0
T25	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	120881	0	0
T2	2367	37	0	0
T3	3417	37	0	0
T4	6542	0	0	0
T5	5203	153	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	0	0	0
T9	2486	37	0	0
T10	3077	37	0	0
T11	3364	81	0	0
T14	0	38	0	0
T23	0	317	0	0
T24	0	108	0	0
T25	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	6546749	0	0
T1	5152	931	0	0
T2	2367	1424	0	0
T3	3417	2473	0	0
T4	6542	661	0	0
T5	5203	4371	0	0
T6	1806	1187	0	0
T7	3815	891	0	0
T8	10782	10164	0	0
T9	2486	1483	0	0
T10	3077	2135	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	192324	0	0
T2	2367	44	0	0
T3	3417	62	0	0
T4	6542	0	0	0
T5	5203	235	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	0	0	0
T9	2486	65	0	0
T10	3077	67	0	0
T11	3364	143	0	0
T14	0	43	0	0
T23	0	521	0	0
T24	0	171	0	0
T25	0	65	0	0