Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T2 T3 T9 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T2 T3 T9 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T23
1	0	Covered	T9,T14,T49

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52872612	8681	0	0
CascadeEffAonToRstPorAboveRise_A	52872612	8681	0	0
CascadeEffAonToRstPorIoAboveFall_A	50756297	8681	0	0
CascadeEffAonToRstPorIoAboveRise_A	50756297	8681	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25379288	8681	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25379288	8681	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12689251	8681	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12689251	8681	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25378930	8681	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25378930	8681	0	0
CascadeLcToLcAboveFall_A	52872612	21762	0	0
CascadeLcToLcAboveRise_A	52872612	21762	0	0
CascadeLcToLcAonAboveFall_A	1602345	21762	0	0
CascadeLcToLcAonAboveRise_A	1602345	21762	0	0
CascadeLcToLcShadowedAboveFall_A	52872612	21762	0	0
CascadeLcToLcShadowedAboveRise_A	52872612	21762	0	0
CascadePorToAonAboveFall_A	1602345	6851	0	0
CascadeSysToSysAboveFall_A	52872612	21762	0	0
CascadeSysToSysAboveRise_A	52872612	21762	0	0
ScanRstToAonRise_A	1602345	203	0	0
StablePorToAonRise_A	1602345	8681	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11229616	21762	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11229616	21762	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11229616	21762	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11229616	21762	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12689251	21762	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12689251	21762	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11229616	21762	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11229616	21762	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11229616	21762	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11229616	21762	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	8681	0	0
T1	22047	2	0	0
T2	11271	2	0	0
T3	15456	2	0	0
T4	30094	10	0	0
T5	26672	1	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	2	0	0
T10	14421	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	8681	0	0
T1	22047	2	0	0
T2	11271	2	0	0
T3	15456	2	0	0
T4	30094	10	0	0
T5	26672	1	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	2	0	0
T10	14421	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50756297	8681	0	0
T1	21164	2	0	0
T2	10817	2	0	0
T3	14835	2	0	0
T4	28881	10	0	0
T5	25603	1	0	0
T6	7396	1	0	0
T7	15912	2	0	0
T8	43302	1	0	0
T9	10336	2	0	0
T10	13843	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50756297	8681	0	0
T1	21164	2	0	0
T2	10817	2	0	0
T3	14835	2	0	0
T4	28881	10	0	0
T5	25603	1	0	0
T6	7396	1	0	0
T7	15912	2	0	0
T8	43302	1	0	0
T9	10336	2	0	0
T10	13843	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25379288	8681	0	0
T1	10582	2	0	0
T2	5408	2	0	0
T3	7417	2	0	0
T4	14445	10	0	0
T5	12801	1	0	0
T6	3697	1	0	0
T7	7955	2	0	0
T8	21652	1	0	0
T9	5169	2	0	0
T10	6923	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25379288	8681	0	0
T1	10582	2	0	0
T2	5408	2	0	0
T3	7417	2	0	0
T4	14445	10	0	0
T5	12801	1	0	0
T6	3697	1	0	0
T7	7955	2	0	0
T8	21652	1	0	0
T9	5169	2	0	0
T10	6923	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	8681	0	0
T1	5289	2	0	0
T2	2702	2	0	0
T3	3709	2	0	0
T4	7222	10	0	0
T5	6400	1	0	0
T6	1848	1	0	0
T7	3978	2	0	0
T8	10824	1	0	0
T9	2583	2	0	0
T10	3461	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	8681	0	0
T1	5289	2	0	0
T2	2702	2	0	0
T3	3709	2	0	0
T4	7222	10	0	0
T5	6400	1	0	0
T6	1848	1	0	0
T7	3978	2	0	0
T8	10824	1	0	0
T9	2583	2	0	0
T10	3461	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378930	8681	0	0
T1	10581	2	0	0
T2	5407	2	0	0
T3	7417	2	0	0
T4	14452	10	0	0
T5	12801	1	0	0
T6	3697	1	0	0
T7	7956	2	0	0
T8	21652	1	0	0
T9	5168	2	0	0
T10	6922	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378930	8681	0	0
T1	10581	2	0	0
T2	5407	2	0	0
T3	7417	2	0	0
T4	14452	10	0	0
T5	12801	1	0	0
T6	3697	1	0	0
T7	7956	2	0	0
T8	21652	1	0	0
T9	5168	2	0	0
T10	6922	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	21762	0	0
T1	22047	2	0	0
T2	11271	6	0	0
T3	15456	6	0	0
T4	30094	10	0	0
T5	26672	18	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	6	0	0
T10	14421	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	21762	0	0
T1	22047	2	0	0
T2	11271	6	0	0
T3	15456	6	0	0
T4	30094	10	0	0
T5	26672	18	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	6	0	0
T10	14421	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	21762	0	0
T1	661	2	0	0
T2	337	6	0	0
T3	462	6	0	0
T4	906	10	0	0
T5	799	18	0	0
T6	230	1	0	0
T7	495	2	0	0
T8	1352	1	0	0
T9	323	6	0	0
T10	432	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	21762	0	0
T1	661	2	0	0
T2	337	6	0	0
T3	462	6	0	0
T4	906	10	0	0
T5	799	18	0	0
T6	230	1	0	0
T7	495	2	0	0
T8	1352	1	0	0
T9	323	6	0	0
T10	432	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	21762	0	0
T1	22047	2	0	0
T2	11271	6	0	0
T3	15456	6	0	0
T4	30094	10	0	0
T5	26672	18	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	6	0	0
T10	14421	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	21762	0	0
T1	22047	2	0	0
T2	11271	6	0	0
T3	15456	6	0	0
T4	30094	10	0	0
T5	26672	18	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	6	0	0
T10	14421	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	6851	0	0
T1	661	21	0	0
T2	337	1	0	0
T3	462	1	0	0
T4	906	10	0	0
T5	799	1	0	0
T6	230	1	0	0
T7	495	14	0	0
T8	1352	1	0	0
T9	323	1	0	0
T10	432	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	21762	0	0
T1	22047	2	0	0
T2	11271	6	0	0
T3	15456	6	0	0
T4	30094	10	0	0
T5	26672	18	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	6	0	0
T10	14421	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52872612	21762	0	0
T1	22047	2	0	0
T2	11271	6	0	0
T3	15456	6	0	0
T4	30094	10	0	0
T5	26672	18	0	0
T6	7704	1	0	0
T7	16577	2	0	0
T8	45109	1	0	0
T9	10765	6	0	0
T10	14421	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	203	0	0
T3	462	1	0	0
T4	906	0	0	0
T5	799	0	0	0
T6	230	0	0	0
T7	495	0	0	0
T8	1352	0	0	0
T9	323	0	0	0
T10	432	0	0	0
T11	502	0	0	0
T15	902	0	0	0
T23	0	1	0	0
T49	0	3	0	0
T53	0	1	0	0
T79	0	1	0	0
T85	0	4	0	0
T95	0	1	0	0
T96	0	1	0	0
T99	0	1	0	0
T100	0	5	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	8681	0	0
T1	661	2	0	0
T2	337	2	0	0
T3	462	2	0	0
T4	906	10	0	0
T5	799	1	0	0
T6	230	1	0	0
T7	495	2	0	0
T8	1352	1	0	0
T9	323	2	0	0
T10	432	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	21762	0	0
T1	5289	2	0	0
T2	2702	6	0	0
T3	3709	6	0	0
T4	7222	10	0	0
T5	6400	18	0	0
T6	1848	1	0	0
T7	3978	2	0	0
T8	10824	1	0	0
T9	2583	6	0	0
T10	3461	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	21762	0	0
T1	5289	2	0	0
T2	2702	6	0	0
T3	3709	6	0	0
T4	7222	10	0	0
T5	6400	18	0	0
T6	1848	1	0	0
T7	3978	2	0	0
T8	10824	1	0	0
T9	2583	6	0	0
T10	3461	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11229616	21762	0	0
T1	5152	2	0	0
T2	2367	6	0	0
T3	3417	6	0	0
T4	6542	10	0	0
T5	5203	18	0	0
T6	1806	1	0	0
T7	3815	2	0	0
T8	10782	1	0	0
T9	2486	6	0	0
T10	3077	6	0	0