Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T14
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T50
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T50
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T50
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12689251	13891	0	0
gen_assertions[0].RstEnOn_A	12689251	961	0	0
gen_assertions[0].RstNOff_A	12689251	13891	0	0
gen_assertions[0].RstNOn_A	12689251	961	0	0
gen_assertions[1].RstEnOff_A	50756297	12591	0	0
gen_assertions[1].RstEnOn_A	50756297	947	0	0
gen_assertions[1].RstNOff_A	50756297	12591	0	0
gen_assertions[1].RstNOn_A	50756297	947	0	0
gen_assertions[2].RstEnOff_A	25379288	12640	0	0
gen_assertions[2].RstEnOn_A	25379288	946	0	0
gen_assertions[2].RstNOff_A	25379288	12640	0	0
gen_assertions[2].RstNOn_A	25379288	946	0	0
gen_assertions[3].RstEnOff_A	25378930	12670	0	0
gen_assertions[3].RstEnOn_A	25378930	970	0	0
gen_assertions[3].RstNOff_A	25378930	12670	0	0
gen_assertions[3].RstNOn_A	25378930	970	0	0
gen_assertions[4].RstEnOff_A	1602345	21401	0	0
gen_assertions[4].RstEnOn_A	1602345	1071	0	0
gen_assertions[4].RstNOff_A	1602345	21401	0	0
gen_assertions[4].RstNOn_A	1602345	1071	0	0
gen_assertions[5].RstEnOff_A	12689251	14161	0	0
gen_assertions[5].RstEnOn_A	12689251	1106	0	0
gen_assertions[5].RstNOff_A	12689251	14161	0	0
gen_assertions[5].RstNOn_A	12689251	1106	0	0
gen_assertions[6].RstEnOff_A	12689251	14193	0	0
gen_assertions[6].RstEnOn_A	12689251	1148	0	0
gen_assertions[6].RstNOff_A	12689251	14193	0	0
gen_assertions[6].RstNOn_A	12689251	1148	0	0
gen_assertions[7].RstEnOff_A	12689251	14229	0	0
gen_assertions[7].RstEnOn_A	12689251	1181	0	0
gen_assertions[7].RstNOff_A	12689251	14229	0	0
gen_assertions[7].RstNOn_A	12689251	1181	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	13891	0	0
T2	2702	4	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	5	0	0
T9	2583	5	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	1	0	0
T14	0	5	0	0
T23	0	35	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	961	0	0
T5	6400	2	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	5	0	0
T9	2583	1	0	0
T10	3461	0	0	0
T11	4022	1	0	0
T12	8841	1	0	0
T14	0	1	0	0
T15	7190	0	0	0
T24	0	6	0	0
T36	0	1	0	0
T50	0	5	0	0
T54	1707	0	0	0
T82	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	13891	0	0
T2	2702	4	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	5	0	0
T9	2583	5	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	1	0	0
T14	0	5	0	0
T23	0	35	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	961	0	0
T5	6400	2	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	5	0	0
T9	2583	1	0	0
T10	3461	0	0	0
T11	4022	1	0	0
T12	8841	1	0	0
T14	0	1	0	0
T15	7190	0	0	0
T24	0	6	0	0
T36	0	1	0	0
T50	0	5	0	0
T54	1707	0	0	0
T82	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50756297	12591	0	0
T2	10817	1	0	0
T3	14835	4	0	0
T4	28881	0	0	0
T5	25603	14	0	0
T6	7396	0	0	0
T7	15912	0	0	0
T8	43302	6	0	0
T9	10336	3	0	0
T10	13843	4	0	0
T11	16097	8	0	0
T12	0	2	0	0
T14	0	2	0	0
T23	0	32	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50756297	947	0	0
T8	43302	6	0	0
T9	10336	0	0	0
T10	13843	0	0	0
T11	16097	0	0	0
T12	35364	2	0	0
T13	20886	0	0	0
T14	18840	1	0	0
T15	28746	0	0	0
T23	57941	0	0	0
T24	0	4	0	0
T39	0	4	0	0
T42	0	1	0	0
T50	0	8	0	0
T54	6830	0	0	0
T78	0	8	0	0
T82	0	8	0	0
T83	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50756297	12591	0	0
T2	10817	1	0	0
T3	14835	4	0	0
T4	28881	0	0	0
T5	25603	14	0	0
T6	7396	0	0	0
T7	15912	0	0	0
T8	43302	6	0	0
T9	10336	3	0	0
T10	13843	4	0	0
T11	16097	8	0	0
T12	0	2	0	0
T14	0	2	0	0
T23	0	32	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50756297	947	0	0
T8	43302	6	0	0
T9	10336	0	0	0
T10	13843	0	0	0
T11	16097	0	0	0
T12	35364	2	0	0
T13	20886	0	0	0
T14	18840	1	0	0
T15	28746	0	0	0
T23	57941	0	0	0
T24	0	4	0	0
T39	0	4	0	0
T42	0	1	0	0
T50	0	8	0	0
T54	6830	0	0	0
T78	0	8	0	0
T82	0	8	0	0
T83	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25379288	12640	0	0
T2	5408	1	0	0
T3	7417	4	0	0
T4	14445	0	0	0
T5	12801	14	0	0
T6	3697	0	0	0
T7	7955	0	0	0
T8	21652	5	0	0
T9	5169	3	0	0
T10	6923	4	0	0
T11	8047	8	0	0
T12	0	4	0	0
T14	0	1	0	0
T23	0	32	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25379288	946	0	0
T8	21652	5	0	0
T9	5169	0	0	0
T10	6923	0	0	0
T11	8047	0	0	0
T12	17682	4	0	0
T13	10443	0	0	0
T14	9420	0	0	0
T15	14379	0	0	0
T23	28966	0	0	0
T39	0	5	0	0
T50	0	9	0	0
T53	0	1	0	0
T54	3415	0	0	0
T78	0	9	0	0
T81	0	1	0	0
T82	0	8	0	0
T83	0	4	0	0
T84	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25379288	12640	0	0
T2	5408	1	0	0
T3	7417	4	0	0
T4	14445	0	0	0
T5	12801	14	0	0
T6	3697	0	0	0
T7	7955	0	0	0
T8	21652	5	0	0
T9	5169	3	0	0
T10	6923	4	0	0
T11	8047	8	0	0
T12	0	4	0	0
T14	0	1	0	0
T23	0	32	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25379288	946	0	0
T8	21652	5	0	0
T9	5169	0	0	0
T10	6923	0	0	0
T11	8047	0	0	0
T12	17682	4	0	0
T13	10443	0	0	0
T14	9420	0	0	0
T15	14379	0	0	0
T23	28966	0	0	0
T39	0	5	0	0
T50	0	9	0	0
T53	0	1	0	0
T54	3415	0	0	0
T78	0	9	0	0
T81	0	1	0	0
T82	0	8	0	0
T83	0	4	0	0
T84	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378930	12670	0	0
T2	5407	1	0	0
T3	7417	4	0	0
T4	14452	0	0	0
T5	12801	14	0	0
T6	3697	0	0	0
T7	7956	0	0	0
T8	21652	8	0	0
T9	5168	4	0	0
T10	6922	4	0	0
T11	8047	8	0	0
T12	0	5	0	0
T14	0	1	0	0
T23	0	32	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378930	970	0	0
T8	21652	8	0	0
T9	5168	1	0	0
T10	6922	0	0	0
T11	8047	0	0	0
T12	17682	5	0	0
T13	10443	0	0	0
T14	9419	0	0	0
T15	14382	0	0	0
T23	28961	0	0	0
T39	0	6	0	0
T42	0	1	0	0
T50	0	9	0	0
T54	3415	0	0	0
T78	0	7	0	0
T81	0	1	0	0
T82	0	10	0	0
T83	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378930	12670	0	0
T2	5407	1	0	0
T3	7417	4	0	0
T4	14452	0	0	0
T5	12801	14	0	0
T6	3697	0	0	0
T7	7956	0	0	0
T8	21652	8	0	0
T9	5168	4	0	0
T10	6922	4	0	0
T11	8047	8	0	0
T12	0	5	0	0
T14	0	1	0	0
T23	0	32	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378930	970	0	0
T8	21652	8	0	0
T9	5168	1	0	0
T10	6922	0	0	0
T11	8047	0	0	0
T12	17682	5	0	0
T13	10443	0	0	0
T14	9419	0	0	0
T15	14382	0	0	0
T23	28961	0	0	0
T39	0	6	0	0
T42	0	1	0	0
T50	0	9	0	0
T54	3415	0	0	0
T78	0	7	0	0
T81	0	1	0	0
T82	0	10	0	0
T83	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	21401	0	0
T1	661	2	0	0
T2	337	6	0	0
T3	462	6	0	0
T4	906	3	0	0
T5	799	17	0	0
T6	230	1	0	0
T7	495	2	0	0
T8	1352	10	0	0
T9	323	6	0	0
T10	432	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	1071	0	0
T8	1352	9	0	0
T9	323	0	0	0
T10	432	0	0	0
T11	502	0	0	0
T12	1104	6	0	0
T13	652	0	0	0
T14	588	0	0	0
T15	902	0	0	0
T23	1888	0	0	0
T39	0	6	0	0
T50	0	11	0	0
T54	212	0	0	0
T78	0	10	0	0
T82	0	11	0	0
T83	0	5	0	0
T84	0	5	0	0
T85	0	4	0	0
T86	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	21401	0	0
T1	661	2	0	0
T2	337	6	0	0
T3	462	6	0	0
T4	906	3	0	0
T5	799	17	0	0
T6	230	1	0	0
T7	495	2	0	0
T8	1352	10	0	0
T9	323	6	0	0
T10	432	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602345	1071	0	0
T8	1352	9	0	0
T9	323	0	0	0
T10	432	0	0	0
T11	502	0	0	0
T12	1104	6	0	0
T13	652	0	0	0
T14	588	0	0	0
T15	902	0	0	0
T23	1888	0	0	0
T39	0	6	0	0
T50	0	11	0	0
T54	212	0	0	0
T78	0	10	0	0
T82	0	11	0	0
T83	0	5	0	0
T84	0	5	0	0
T85	0	4	0	0
T86	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	14161	0	0
T2	2702	4	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	9	0	0
T9	2583	5	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	7	0	0
T14	0	4	0	0
T23	0	35	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	1106	0	0
T8	10824	9	0	0
T9	2583	1	0	0
T10	3461	0	0	0
T11	4022	0	0	0
T12	8841	7	0	0
T13	5221	0	0	0
T14	4708	0	0	0
T15	7190	0	0	0
T23	14477	0	0	0
T39	0	7	0	0
T50	0	10	0	0
T53	0	1	0	0
T54	1707	0	0	0
T75	0	1	0	0
T78	0	14	0	0
T82	0	12	0	0
T83	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	14161	0	0
T2	2702	4	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	9	0	0
T9	2583	5	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	7	0	0
T14	0	4	0	0
T23	0	35	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	1106	0	0
T8	10824	9	0	0
T9	2583	1	0	0
T10	3461	0	0	0
T11	4022	0	0	0
T12	8841	7	0	0
T13	5221	0	0	0
T14	4708	0	0	0
T15	7190	0	0	0
T23	14477	0	0	0
T39	0	7	0	0
T50	0	10	0	0
T53	0	1	0	0
T54	1707	0	0	0
T75	0	1	0	0
T78	0	14	0	0
T82	0	12	0	0
T83	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	14193	0	0
T2	2702	5	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	10	0	0
T9	2583	4	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	6	0	0
T14	0	4	0	0
T23	0	35	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	1148	0	0
T2	2702	1	0	0
T3	3709	0	0	0
T4	7222	0	0	0
T5	6400	0	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	10	0	0
T9	2583	0	0	0
T10	3461	0	0	0
T11	4022	0	0	0
T12	0	6	0	0
T39	0	9	0	0
T50	0	11	0	0
T75	0	1	0	0
T78	0	12	0	0
T82	0	10	0	0
T83	0	7	0	0
T84	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	14193	0	0
T2	2702	5	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	10	0	0
T9	2583	4	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	6	0	0
T14	0	4	0	0
T23	0	35	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	1148	0	0
T2	2702	1	0	0
T3	3709	0	0	0
T4	7222	0	0	0
T5	6400	0	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	10	0	0
T9	2583	0	0	0
T10	3461	0	0	0
T11	4022	0	0	0
T12	0	6	0	0
T39	0	9	0	0
T50	0	11	0	0
T75	0	1	0	0
T78	0	12	0	0
T82	0	10	0	0
T83	0	7	0	0
T84	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	14229	0	0
T2	2702	4	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	11	0	0
T9	2583	4	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	8	0	0
T14	0	4	0	0
T23	0	35	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	1181	0	0
T8	10824	11	0	0
T9	2583	0	0	0
T10	3461	0	0	0
T11	4022	0	0	0
T12	8841	8	0	0
T13	5221	0	0	0
T14	4708	0	0	0
T15	7190	0	0	0
T23	14477	0	0	0
T39	0	10	0	0
T50	0	12	0	0
T53	0	1	0	0
T54	1707	0	0	0
T78	0	16	0	0
T82	0	13	0	0
T83	0	9	0	0
T84	0	9	0	0
T85	0	3	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	14229	0	0
T2	2702	4	0	0
T3	3709	4	0	0
T4	7222	0	0	0
T5	6400	17	0	0
T6	1848	0	0	0
T7	3978	0	0	0
T8	10824	11	0	0
T9	2583	4	0	0
T10	3461	4	0	0
T11	4022	9	0	0
T12	0	8	0	0
T14	0	4	0	0
T23	0	35	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689251	1181	0	0
T8	10824	11	0	0
T9	2583	0	0	0
T10	3461	0	0	0
T11	4022	0	0	0
T12	8841	8	0	0
T13	5221	0	0	0
T14	4708	0	0	0
T15	7190	0	0	0
T23	14477	0	0	0
T39	0	10	0	0
T50	0	12	0	0
T53	0	1	0	0
T54	1707	0	0	0
T78	0	16	0	0
T82	0	13	0	0
T83	0	9	0	0
T84	0	9	0	0
T85	0	3	0	0