Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11992193	7599	0	0
alert_regwen_rd_A	11992193	4794	0	0
cpu_regwen_rd_A	11992193	4855	0	0
sw_rst_ctrl_n_0_rd_A	11992193	8857	0	0
sw_rst_ctrl_n_1_rd_A	11992193	8497	0	0
sw_rst_ctrl_n_2_rd_A	11992193	8424	0	0
sw_rst_ctrl_n_3_rd_A	11992193	8413	0	0
sw_rst_ctrl_n_4_rd_A	11992193	8747	0	0
sw_rst_ctrl_n_5_rd_A	11992193	8493	0	0
sw_rst_ctrl_n_6_rd_A	11992193	8748	0	0
sw_rst_ctrl_n_7_rd_A	11992193	8778	0	0
sw_rst_regwen_0_rd_A	11992193	5048	0	0
sw_rst_regwen_1_rd_A	11992193	5051	0	0
sw_rst_regwen_2_rd_A	11992193	5046	0	0
sw_rst_regwen_3_rd_A	11992193	5118	0	0
sw_rst_regwen_4_rd_A	11992193	5053	0	0
sw_rst_regwen_5_rd_A	11992193	5096	0	0
sw_rst_regwen_6_rd_A	11992193	5144	0	0
sw_rst_regwen_7_rd_A	11992193	5243	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	7599	0	0
T61	8875	323	0	0
T62	18095	3	0	0
T65	4422	20	0	0
T69	3777	97	0	0
T70	3314	294	0	0
T72	11037	2	0	0
T87	4449	23	0	0
T88	21999	1	0	0
T89	4456	13	0	0
T93	9149	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	4794	0	0
T21	3939	0	0	0
T68	176907	0	0	0
T73	390202	0	0	0
T96	42193	80	0	0
T97	30609	57	0	0
T102	0	229	0	0
T106	0	254	0	0
T109	0	55	0	0
T125	0	74	0	0
T126	0	57	0	0
T127	0	26	0	0
T128	0	52	0	0
T129	0	65	0	0
T130	1414	0	0	0
T131	6775	0	0	0
T132	5222	0	0	0
T133	3591	0	0	0
T134	3998	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	4855	0	0
T21	3939	0	0	0
T68	176907	0	0	0
T73	390202	0	0	0
T96	42193	81	0	0
T97	30609	34	0	0
T102	0	180	0	0
T106	0	238	0	0
T109	0	87	0	0
T125	0	77	0	0
T126	0	32	0	0
T127	0	42	0	0
T128	0	51	0	0
T129	0	54	0	0
T130	1414	0	0	0
T131	6775	0	0	0
T132	5222	0	0	0
T133	3591	0	0	0
T134	3998	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8857	0	0
T5	5203	57	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	167	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	25	0	0
T12	8774	126	0	0
T15	6507	0	0	0
T36	0	45	0	0
T54	1616	0	0	0
T75	0	16	0	0
T81	0	6	0	0
T84	0	158	0	0
T103	0	10	0	0
T135	0	19	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8497	0	0
T5	5203	58	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	151	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	19	0	0
T12	8774	127	0	0
T15	6507	0	0	0
T36	0	30	0	0
T54	1616	0	0	0
T75	0	8	0	0
T81	0	14	0	0
T84	0	143	0	0
T103	0	12	0	0
T135	0	41	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8424	0	0
T5	5203	61	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	184	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	22	0	0
T12	8774	135	0	0
T15	6507	0	0	0
T36	0	45	0	0
T54	1616	0	0	0
T75	0	10	0	0
T81	0	19	0	0
T84	0	92	0	0
T103	0	14	0	0
T135	0	30	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8413	0	0
T5	5203	72	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	160	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	28	0	0
T12	8774	95	0	0
T15	6507	0	0	0
T36	0	33	0	0
T54	1616	0	0	0
T75	0	15	0	0
T81	0	13	0	0
T84	0	128	0	0
T103	0	14	0	0
T135	0	23	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8747	0	0
T5	5203	78	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	165	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	25	0	0
T12	8774	129	0	0
T15	6507	0	0	0
T36	0	37	0	0
T54	1616	0	0	0
T75	0	7	0	0
T81	0	22	0	0
T84	0	128	0	0
T103	0	21	0	0
T135	0	15	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8493	0	0
T5	5203	45	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	188	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	49	0	0
T12	8774	118	0	0
T15	6507	0	0	0
T36	0	37	0	0
T54	1616	0	0	0
T75	0	24	0	0
T81	0	12	0	0
T84	0	157	0	0
T103	0	31	0	0
T135	0	31	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8748	0	0
T5	5203	60	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	155	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	46	0	0
T12	8774	120	0	0
T15	6507	0	0	0
T36	0	56	0	0
T54	1616	0	0	0
T75	0	12	0	0
T81	0	16	0	0
T84	0	149	0	0
T103	0	4	0	0
T135	0	40	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	8778	0	0
T5	5203	41	0	0
T6	1806	0	0	0
T7	3815	0	0	0
T8	10782	150	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	24	0	0
T12	8774	125	0	0
T15	6507	0	0	0
T36	0	33	0	0
T54	1616	0	0	0
T75	0	19	0	0
T81	0	14	0	0
T84	0	113	0	0
T103	0	14	0	0
T135	0	29	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5048	0	0
T8	10782	20	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	34	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	1	0	0
T81	0	10	0	0
T84	0	36	0	0
T96	0	70	0	0
T97	0	36	0	0
T102	0	216	0	0
T132	0	1	0	0
T136	0	30	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5051	0	0
T8	10782	35	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	17	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	5	0	0
T81	0	11	0	0
T84	0	36	0	0
T96	0	76	0	0
T97	0	35	0	0
T102	0	199	0	0
T132	0	2	0	0
T136	0	32	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5046	0	0
T8	10782	31	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	33	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	7	0	0
T81	0	3	0	0
T84	0	30	0	0
T96	0	80	0	0
T97	0	28	0	0
T102	0	175	0	0
T132	0	7	0	0
T136	0	43	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5118	0	0
T8	10782	44	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	41	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	10	0	0
T81	0	9	0	0
T84	0	36	0	0
T96	0	75	0	0
T97	0	43	0	0
T102	0	203	0	0
T132	0	1	0	0
T136	0	23	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5053	0	0
T8	10782	37	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	33	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	3	0	0
T81	0	11	0	0
T84	0	34	0	0
T96	0	71	0	0
T97	0	47	0	0
T102	0	156	0	0
T132	0	7	0	0
T136	0	37	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5096	0	0
T8	10782	29	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	29	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T81	0	12	0	0
T84	0	22	0	0
T96	0	71	0	0
T97	0	57	0	0
T102	0	205	0	0
T106	0	223	0	0
T132	0	2	0	0
T136	0	28	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5144	0	0
T8	10782	39	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	27	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	11	0	0
T81	0	11	0	0
T84	0	21	0	0
T96	0	94	0	0
T97	0	46	0	0
T102	0	172	0	0
T132	0	3	0	0
T136	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11992193	5243	0	0
T8	10782	29	0	0
T9	2486	0	0	0
T10	3077	0	0	0
T11	3364	0	0	0
T12	8774	29	0	0
T13	5106	0	0	0
T14	4419	0	0	0
T15	6507	0	0	0
T23	10844	0	0	0
T54	1616	0	0	0
T75	0	4	0	0
T81	0	3	0	0
T84	0	31	0	0
T96	0	84	0	0
T97	0	34	0	0
T102	0	184	0	0
T132	0	8	0	0
T136	0	30	0	0