Unified Coverage Report :: Module :: rstmgr_crash_info

Module : rstmgr_crash_info

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_crash_info.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_alert_info	100.00	100.00				100.00	100.00
tb.dut.u_cpu_info	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_alert_info

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cpu_info

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : rstmgr_crash_info ( parameter CrashDumpWidth=276,CrashStoreSlot=9,SlotCntWidth=4,TotalWidth=288 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_alert_info

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	32	4	4	100.00
ALWAYS	40	2	2	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	45	1	1	100.00

31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                slots_q <= '0;
           Tests:       T1 T2 T3 
34         1/1              end else if (dump_capture_i) begin
           Tests:       T1 T2 T3 
35         1/1                slots_q <= TotalWidth'(dump_i);
           Tests:       T2 T3 T5 
36                          end
                        MISSING_ELSE
37                        end
38                      
39                        always_comb begin
40         1/1              slots = '0;
           Tests:       T2 T3 T5 
41         1/1              slots[CrashStoreSlot-1:0] = slots_q;
           Tests:       T2 T3 T5 
42                        end
43                      
44         unreachable    assign slots_cnt_o = CrashStoreSlot[IdxWidth-1:0];
45         1/1            assign slot_o = slots[slot_sel_i[SlotCntWidth-1:0]];
           Tests:       T2 T3 T5 

---

Line Coverage for Module : rstmgr_crash_info ( parameter CrashDumpWidth=225,CrashStoreSlot=8,SlotCntWidth=3,TotalWidth=256 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_cpu_info

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	32	4	4	100.00
ALWAYS	40	2	2	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	51	0	0

31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                slots_q <= '0;
           Tests:       T1 T2 T3 
34         1/1              end else if (dump_capture_i) begin
           Tests:       T1 T2 T3 
35         1/1                slots_q <= TotalWidth'(dump_i);
           Tests:       T2 T3 T5 
36                          end
                        MISSING_ELSE
37                        end
38                      
39                        always_comb begin
40         1/1              slots = '0;
           Tests:       T2 T3 T5 
41         1/1              slots[CrashStoreSlot-1:0] = slots_q;
           Tests:       T2 T3 T5 
42                        end
43                      
44         unreachable    assign slots_cnt_o = CrashStoreSlot[IdxWidth-1:0];
45         1/1            assign slot_o = slots[slot_sel_i[SlotCntWidth-1:0]];
           Tests:       T2 T3 T5 
46                      
47                        if (SlotCntWidth < IdxWidth) begin : gen_tieoffs
48                          //VCS coverage off
49                          // pragma coverage off
50                          logic [IdxWidth-SlotCntWidth-1:0] unused_idx;
51         unreachable      assign unused_idx = slot_sel_i[IdxWidth-1:SlotCntWidth];

---

Branch Coverage for Module : rstmgr_crash_info

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               slots_q <= '0;
                 ==>
34             end else if (dump_capture_i) begin
                        -2-  
35               slots_q <= TotalWidth'(dump_i);
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_crash_info

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntStoreSlot_A	1010	1010	0	0
CntWidth_A	1010	1010	0	0

CntStoreSlot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

CntWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.u_alert_info

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	32	4	4	100.00
ALWAYS	40	2	2	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	45	1	1	100.00

31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                slots_q <= '0;
           Tests:       T1 T2 T3 
34         1/1              end else if (dump_capture_i) begin
           Tests:       T1 T2 T3 
35         1/1                slots_q <= TotalWidth'(dump_i);
           Tests:       T2 T3 T5 
36                          end
                        MISSING_ELSE
37                        end
38                      
39                        always_comb begin
40         1/1              slots = '0;
           Tests:       T2 T3 T5 
41         1/1              slots[CrashStoreSlot-1:0] = slots_q;
           Tests:       T2 T3 T5 
42                        end
43                      
44         unreachable    assign slots_cnt_o = CrashStoreSlot[IdxWidth-1:0];
45         1/1            assign slot_o = slots[slot_sel_i[SlotCntWidth-1:0]];
           Tests:       T2 T3 T5 

---

Branch Coverage for Instance : tb.dut.u_alert_info

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               slots_q <= '0;
                 ==>
34             end else if (dump_capture_i) begin
                        -2-  
35               slots_q <= TotalWidth'(dump_i);
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_alert_info

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntStoreSlot_A	505	505	0	0
CntWidth_A	505	505	0	0

CntStoreSlot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505	505	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

CntWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505	505	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_cpu_info

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	32	4	4	100.00
ALWAYS	40	2	2	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	51	0	0

31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                slots_q <= '0;
           Tests:       T1 T2 T3 
34         1/1              end else if (dump_capture_i) begin
           Tests:       T1 T2 T3 
35         1/1                slots_q <= TotalWidth'(dump_i);
           Tests:       T2 T3 T5 
36                          end
                        MISSING_ELSE
37                        end
38                      
39                        always_comb begin
40         1/1              slots = '0;
           Tests:       T2 T3 T5 
41         1/1              slots[CrashStoreSlot-1:0] = slots_q;
           Tests:       T2 T3 T5 
42                        end
43                      
44         unreachable    assign slots_cnt_o = CrashStoreSlot[IdxWidth-1:0];
45         1/1            assign slot_o = slots[slot_sel_i[SlotCntWidth-1:0]];
           Tests:       T2 T3 T5 
46                      
47                        if (SlotCntWidth < IdxWidth) begin : gen_tieoffs
48                          //VCS coverage off
49                          // pragma coverage off
50                          logic [IdxWidth-SlotCntWidth-1:0] unused_idx;
51         unreachable      assign unused_idx = slot_sel_i[IdxWidth-1:SlotCntWidth];

---

Branch Coverage for Instance : tb.dut.u_cpu_info

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               slots_q <= '0;
                 ==>
34             end else if (dump_capture_i) begin
                        -2-  
35               slots_q <= TotalWidth'(dump_i);
                 ==>
36             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_cpu_info

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntStoreSlot_A	505	505	0	0
CntWidth_A	505	505	0	0

CntStoreSlot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505	505	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

CntWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505	505	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0