Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	619190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

367523

1

T2

22

T3

7

T4

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526235	1			T1	1		T2	31		T4	99
values[0x0]	230437	1			T2	20		T3	9		T4	55
values[0x1]	230041	1			T2	14		T3	9		T4	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	520111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

466602

1

T2

24

T3

8

T4

92

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3330	1			T4	2		T67	1		T57	12
valid_sources[0x01]	5486	1			T4	1		T10	130		T11	1
valid_sources[0x02]	3309	1			T4	1		T7	2		T13	2
valid_sources[0x03]	2708	1			T4	5		T7	2		T11	1
valid_sources[0x04]	2909	1			T5	2		T13	1		T67	1
valid_sources[0x05]	4416	1			T7	3		T11	3		T14	1
valid_sources[0x06]	3078	1			T2	6		T4	2		T13	4
valid_sources[0x07]	4379	1			T4	1		T7	3		T11	1
valid_sources[0x08]	3721	1			T2	1		T4	2		T7	4
valid_sources[0x09]	4585	1			T4	1		T5	1		T7	19
valid_sources[0x0a]	3052	1			T5	6		T7	1		T13	1
valid_sources[0x0b]	3053	1			T2	3		T5	3		T13	3
valid_sources[0x0c]	7416	1			T5	4		T7	2		T57	6
valid_sources[0x0d]	2926	1			T4	2		T5	2		T7	8
valid_sources[0x0e]	3098	1			T5	1		T7	3		T11	1
valid_sources[0x0f]	3388	1			T4	1		T5	6		T7	11
valid_sources[0x10]	4863	1			T7	3		T13	6		T14	1
valid_sources[0x11]	2903	1			T7	5		T11	1		T14	2
valid_sources[0x12]	3161	1			T2	3		T7	13		T9	1
valid_sources[0x13]	4035	1			T7	1		T13	2		T14	1
valid_sources[0x14]	3506	1			T7	5		T11	3		T67	3
valid_sources[0x15]	3733	1			T5	2		T11	3		T67	4
valid_sources[0x16]	3029	1			T5	2		T7	2		T11	3
valid_sources[0x17]	4455	1			T4	1		T5	9		T7	10
valid_sources[0x18]	3213	1			T4	1		T7	2		T11	2
valid_sources[0x19]	2972	1			T5	1		T7	7		T14	6
valid_sources[0x1a]	6265	1			T4	1		T5	4		T7	2
valid_sources[0x1b]	5108	1			T5	4		T7	5		T57	17
valid_sources[0x1c]	3904	1			T5	1		T7	1		T11	2
valid_sources[0x1d]	3610	1			T4	2		T5	2		T7	2
valid_sources[0x1e]	3142	1			T5	3		T7	3		T67	2
valid_sources[0x1f]	3148	1			T5	2		T13	3		T67	1
valid_sources[0x20]	2648	1			T5	1		T13	1		T67	9
valid_sources[0x21]	4181	1			T7	5		T13	1		T14	3
valid_sources[0x22]	3661	1			T7	4		T13	5		T67	6
valid_sources[0x23]	3099	1			T5	1		T11	1		T13	1
valid_sources[0x24]	3672	1			T4	1		T5	1		T7	6
valid_sources[0x25]	3493	1			T7	2		T11	4		T14	2
valid_sources[0x26]	3220	1			T4	1		T7	1		T67	2
valid_sources[0x27]	4284	1			T4	4		T5	1		T7	3
valid_sources[0x28]	4456	1			T14	2		T67	2		T57	12
valid_sources[0x29]	3190	1			T5	1		T11	1		T13	2
valid_sources[0x2a]	5447	1			T4	1		T7	8		T67	2
valid_sources[0x2b]	3886	1			T2	3		T5	3		T7	6
valid_sources[0x2c]	4056	1			T5	3		T14	2		T67	12
valid_sources[0x2d]	3856	1			T2	1		T5	2		T13	1
valid_sources[0x2e]	4308	1			T2	2		T5	5		T11	5
valid_sources[0x2f]	3940	1			T7	9		T67	4		T57	6
valid_sources[0x30]	3022	1			T4	3		T7	3		T11	1
valid_sources[0x31]	4332	1			T3	18		T67	4		T57	8
valid_sources[0x32]	4377	1			T11	1		T67	4		T57	11
valid_sources[0x33]	3835	1			T5	3		T11	2		T67	6
valid_sources[0x34]	4161	1			T4	1		T7	3		T9	1
valid_sources[0x35]	2686	1			T4	1		T5	2		T7	5
valid_sources[0x36]	3511	1			T5	2		T7	3		T14	1
valid_sources[0x37]	3587	1			T4	3		T11	1		T13	1
valid_sources[0x38]	3731	1			T4	1		T5	10		T11	2
valid_sources[0x39]	3670	1			T4	2		T7	1		T67	4
valid_sources[0x3a]	4093	1			T5	2		T7	6		T13	1
valid_sources[0x3b]	3187	1			T5	1		T11	1		T67	2
valid_sources[0x3c]	6549	1			T4	3		T7	2		T11	3
valid_sources[0x3d]	6189	1			T4	5		T5	1		T7	6
valid_sources[0x3e]	3575	1			T4	3		T5	2		T11	1
valid_sources[0x3f]	8812	1			T5	2		T7	5		T9	1
valid_sources[0x40]	3320	1			T4	5		T7	2		T13	4
valid_sources[0x41]	4282	1			T4	1		T5	2		T13	3
valid_sources[0x42]	2952	1			T5	2		T7	2		T13	2
valid_sources[0x43]	3508	1			T5	4		T7	9		T57	10
valid_sources[0x44]	5974	1			T4	1		T5	4		T11	3
valid_sources[0x45]	3551	1			T4	1		T5	1		T7	3
valid_sources[0x46]	4093	1			T4	4		T7	10		T13	5
valid_sources[0x47]	3628	1			T7	14		T13	1		T67	1
valid_sources[0x48]	4061	1			T4	1		T7	2		T67	5
valid_sources[0x49]	3353	1			T13	5		T67	6		T24	12
valid_sources[0x4a]	6914	1			T5	2		T7	3		T14	2
valid_sources[0x4b]	8217	1			T4	1		T5	2		T11	3
valid_sources[0x4c]	3447	1			T4	1		T7	1		T67	3
valid_sources[0x4d]	4074	1			T4	1		T5	4		T13	1
valid_sources[0x4e]	3165	1			T11	2		T67	10		T24	2
valid_sources[0x4f]	3540	1			T7	2		T11	2		T13	1
valid_sources[0x50]	3554	1			T5	5		T7	9		T13	8
valid_sources[0x51]	3225	1			T2	3		T5	4		T7	8
valid_sources[0x52]	6869	1			T4	1		T5	3		T7	2
valid_sources[0x53]	6971	1			T11	2		T67	4		T57	6
valid_sources[0x54]	3697	1			T4	1		T5	3		T11	1
valid_sources[0x55]	2644	1			T5	2		T7	6		T11	1
valid_sources[0x56]	3917	1			T5	1		T7	2		T57	11
valid_sources[0x57]	3301	1			T5	2		T7	2		T13	4
valid_sources[0x58]	3602	1			T7	4		T11	1		T14	1
valid_sources[0x59]	3031	1			T4	2		T13	1		T67	5
valid_sources[0x5a]	3687	1			T4	3		T5	2		T7	2
valid_sources[0x5b]	3696	1			T7	3		T13	2		T14	1
valid_sources[0x5c]	3573	1			T5	2		T11	1		T14	1
valid_sources[0x5d]	9704	1			T7	3		T11	2		T67	8
valid_sources[0x5e]	3201	1			T5	3		T7	10		T11	1
valid_sources[0x5f]	3714	1			T4	3		T5	1		T57	10
valid_sources[0x60]	3927	1			T5	1		T7	2		T13	1
valid_sources[0x61]	4488	1			T4	2		T7	21		T11	3
valid_sources[0x62]	4240	1			T7	18		T11	3		T67	3
valid_sources[0x63]	3435	1			T4	3		T11	3		T13	5
valid_sources[0x64]	3882	1			T4	2		T5	3		T13	7
valid_sources[0x65]	3961	1			T5	1		T7	1		T9	1
valid_sources[0x66]	2705	1			T2	1		T5	2		T11	1
valid_sources[0x67]	6368	1			T4	1		T7	1		T11	2
valid_sources[0x68]	2838	1			T4	1		T7	6		T67	2
valid_sources[0x69]	3194	1			T2	1		T5	2		T57	9
valid_sources[0x6a]	3421	1			T4	1		T5	2		T7	1
valid_sources[0x6b]	3453	1			T4	1		T5	3		T7	12
valid_sources[0x6c]	4060	1			T5	8		T11	3		T13	2
valid_sources[0x6d]	3201	1			T1	1		T4	1		T7	15
valid_sources[0x6e]	3014	1			T4	1		T5	1		T7	5
valid_sources[0x6f]	3709	1			T7	2		T67	2		T24	8
valid_sources[0x70]	3500	1			T5	3		T7	8		T11	2
valid_sources[0x71]	3684	1			T4	1		T7	6		T11	2
valid_sources[0x72]	3376	1			T5	1		T7	10		T13	1
valid_sources[0x73]	3212	1			T4	3		T5	2		T7	9
valid_sources[0x74]	4554	1			T5	3		T11	3		T13	2
valid_sources[0x75]	3256	1			T4	1		T5	3		T14	1
valid_sources[0x76]	3859	1			T4	1		T5	1		T7	15
valid_sources[0x77]	3824	1			T7	7		T13	2		T67	8
valid_sources[0x78]	4081	1			T4	1		T5	2		T7	14
valid_sources[0x79]	4168	1			T4	1		T7	5		T13	2
valid_sources[0x7a]	3545	1			T4	3		T7	8		T11	1
valid_sources[0x7b]	2951	1			T4	1		T8	1		T11	1
valid_sources[0x7c]	2911	1			T4	1		T7	10		T11	1
valid_sources[0x7d]	3424	1			T7	6		T13	1		T57	11
valid_sources[0x7e]	3755	1			T13	11		T14	2		T67	3
valid_sources[0x7f]	4430	1			T4	1		T5	2		T13	1
valid_sources[0x80]	2726	1			T2	2		T67	5		T57	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

246259

1

T2

16

T4

45

T5

80

values[0x0]

all_enables

biggest_size

79577

1

T2

3

T3

5

T4

22

values[0x1]

all_enables

biggest_size

41687

1

T2

3

T3

2

T4

13