Unified Coverage Report :: Module Instance :: tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Module Instance : tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3