Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T23,T66
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T66
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T13,T23
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T13
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T66,T67
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T13
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T23,T66
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12928335	14100	0	0
gen_assertions[0].RstEnOn_A	12928335	1087	0	0
gen_assertions[0].RstNOff_A	12928335	14100	0	0
gen_assertions[0].RstNOn_A	12928335	1087	0	0
gen_assertions[1].RstEnOff_A	51712842	12716	0	0
gen_assertions[1].RstEnOn_A	51712842	1009	0	0
gen_assertions[1].RstNOff_A	51712842	12716	0	0
gen_assertions[1].RstNOn_A	51712842	1009	0	0
gen_assertions[2].RstEnOff_A	25857601	12803	0	0
gen_assertions[2].RstEnOn_A	25857601	1034	0	0
gen_assertions[2].RstNOff_A	25857601	12803	0	0
gen_assertions[2].RstNOn_A	25857601	1034	0	0
gen_assertions[3].RstEnOff_A	25857430	12838	0	0
gen_assertions[3].RstEnOn_A	25857430	1066	0	0
gen_assertions[3].RstNOff_A	25857430	12838	0	0
gen_assertions[3].RstNOn_A	25857430	1066	0	0
gen_assertions[4].RstEnOff_A	1633692	21561	0	0
gen_assertions[4].RstEnOn_A	1633692	1118	0	0
gen_assertions[4].RstNOff_A	1633692	21561	0	0
gen_assertions[4].RstNOn_A	1633692	1118	0	0
gen_assertions[5].RstEnOff_A	12928335	14316	0	0
gen_assertions[5].RstEnOn_A	12928335	1154	0	0
gen_assertions[5].RstNOff_A	12928335	14316	0	0
gen_assertions[5].RstNOn_A	12928335	1154	0	0
gen_assertions[6].RstEnOff_A	12928335	14378	0	0
gen_assertions[6].RstEnOn_A	12928335	1225	0	0
gen_assertions[6].RstNOff_A	12928335	14378	0	0
gen_assertions[6].RstNOn_A	12928335	1225	0	0
gen_assertions[7].RstEnOff_A	12928335	14441	0	0
gen_assertions[7].RstEnOn_A	12928335	1275	0	0
gen_assertions[7].RstNOff_A	12928335	14441	0	0
gen_assertions[7].RstNOn_A	12928335	1275	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14100	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	4	0	0
T6	7197	0	0	0
T7	7807	5	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1087	0	0
T2	1631	2	0	0
T3	1788	0	0	0
T4	3444	0	0	0
T5	2996	0	0	0
T6	7197	0	0	0
T7	7807	5	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T14	0	1	0	0
T66	0	6	0	0
T67	0	2	0	0
T106	0	4	0	0
T107	0	10	0	0
T108	0	1	0	0
T109	0	2	0	0
T110	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14100	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	4	0	0
T6	7197	0	0	0
T7	7807	5	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1087	0	0
T2	1631	2	0	0
T3	1788	0	0	0
T4	3444	0	0	0
T5	2996	0	0	0
T6	7197	0	0	0
T7	7807	5	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T14	0	1	0	0
T66	0	6	0	0
T67	0	2	0	0
T106	0	4	0	0
T107	0	10	0	0
T108	0	1	0	0
T109	0	2	0	0
T110	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51712842	12716	0	0
T2	6531	3	0	0
T3	7160	0	0	0
T4	13783	4	0	0
T5	11992	4	0	0
T6	28795	0	0	0
T7	31233	5	0	0
T8	15074	0	0	0
T9	6152	0	0	0
T10	11790	5	0	0
T11	9730	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	3	0	0
T23	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51712842	1009	0	0
T7	31233	5	0	0
T8	15074	0	0	0
T9	6152	0	0	0
T10	11790	0	0	0
T11	9730	0	0	0
T12	15127	0	0	0
T13	18915	0	0	0
T14	14815	0	0	0
T22	14063	0	0	0
T23	0	1	0	0
T25	28893	0	0	0
T66	0	6	0	0
T67	0	3	0	0
T104	0	1	0	0
T106	0	5	0	0
T107	0	2	0	0
T108	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51712842	12716	0	0
T2	6531	3	0	0
T3	7160	0	0	0
T4	13783	4	0	0
T5	11992	4	0	0
T6	28795	0	0	0
T7	31233	5	0	0
T8	15074	0	0	0
T9	6152	0	0	0
T10	11790	5	0	0
T11	9730	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	3	0	0
T23	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51712842	1009	0	0
T7	31233	5	0	0
T8	15074	0	0	0
T9	6152	0	0	0
T10	11790	0	0	0
T11	9730	0	0	0
T12	15127	0	0	0
T13	18915	0	0	0
T14	14815	0	0	0
T22	14063	0	0	0
T23	0	1	0	0
T25	28893	0	0	0
T66	0	6	0	0
T67	0	3	0	0
T104	0	1	0	0
T106	0	5	0	0
T107	0	2	0	0
T108	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857601	12803	0	0
T2	3264	3	0	0
T3	3579	0	0	0
T4	6892	4	0	0
T5	5993	5	0	0
T6	14390	0	0	0
T7	15616	6	0	0
T8	7537	0	0	0
T9	3075	0	0	0
T10	5895	5	0	0
T11	4863	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	3	0	0
T23	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857601	1034	0	0
T5	5993	1	0	0
T6	14390	0	0	0
T7	15616	6	0	0
T8	7537	0	0	0
T9	3075	0	0	0
T10	5895	0	0	0
T11	4863	0	0	0
T12	7563	0	0	0
T13	9455	0	0	0
T25	14448	0	0	0
T51	0	3	0	0
T63	0	8	0	0
T66	0	7	0	0
T67	0	4	0	0
T106	0	2	0	0
T108	0	4	0	0
T111	0	2	0	0
T113	0	5	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857601	12803	0	0
T2	3264	3	0	0
T3	3579	0	0	0
T4	6892	4	0	0
T5	5993	5	0	0
T6	14390	0	0	0
T7	15616	6	0	0
T8	7537	0	0	0
T9	3075	0	0	0
T10	5895	5	0	0
T11	4863	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	3	0	0
T23	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857601	1034	0	0
T5	5993	1	0	0
T6	14390	0	0	0
T7	15616	6	0	0
T8	7537	0	0	0
T9	3075	0	0	0
T10	5895	0	0	0
T11	4863	0	0	0
T12	7563	0	0	0
T13	9455	0	0	0
T25	14448	0	0	0
T51	0	3	0	0
T63	0	8	0	0
T66	0	7	0	0
T67	0	4	0	0
T106	0	2	0	0
T108	0	4	0	0
T111	0	2	0	0
T113	0	5	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857430	12838	0	0
T2	3264	3	0	0
T3	3579	0	0	0
T4	6894	4	0	0
T5	5993	4	0	0
T6	14394	0	0	0
T7	15616	7	0	0
T8	7537	0	0	0
T9	3076	0	0	0
T10	5894	5	0	0
T11	4864	4	0	0
T13	0	5	0	0
T14	0	8	0	0
T22	0	3	0	0
T23	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857430	1066	0	0
T7	15616	7	0	0
T8	7537	0	0	0
T9	3076	0	0	0
T10	5894	0	0	0
T11	4864	0	0	0
T12	7563	0	0	0
T13	9455	1	0	0
T14	7407	0	0	0
T22	7036	0	0	0
T23	0	1	0	0
T25	14452	0	0	0
T66	0	8	0	0
T67	0	5	0	0
T104	0	1	0	0
T108	0	4	0	0
T111	0	3	0	0
T112	0	1	0	0
T113	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857430	12838	0	0
T2	3264	3	0	0
T3	3579	0	0	0
T4	6894	4	0	0
T5	5993	4	0	0
T6	14394	0	0	0
T7	15616	7	0	0
T8	7537	0	0	0
T9	3076	0	0	0
T10	5894	5	0	0
T11	4864	4	0	0
T13	0	5	0	0
T14	0	8	0	0
T22	0	3	0	0
T23	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25857430	1066	0	0
T7	15616	7	0	0
T8	7537	0	0	0
T9	3076	0	0	0
T10	5894	0	0	0
T11	4864	0	0	0
T12	7563	0	0	0
T13	9455	1	0	0
T14	7407	0	0	0
T22	7036	0	0	0
T23	0	1	0	0
T25	14452	0	0	0
T66	0	8	0	0
T67	0	5	0	0
T104	0	1	0	0
T108	0	4	0	0
T111	0	3	0	0
T112	0	1	0	0
T113	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633692	21561	0	0
T1	354	2	0	0
T2	203	4	0	0
T3	222	1	0	0
T4	429	6	0	0
T5	373	7	0	0
T6	901	3	0	0
T7	974	7	0	0
T8	471	2	0	0
T9	190	1	0	0
T10	366	8	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633692	1118	0	0
T5	373	1	0	0
T6	901	0	0	0
T7	974	6	0	0
T8	471	0	0	0
T9	190	0	0	0
T10	366	0	0	0
T11	303	0	0	0
T12	471	0	0	0
T13	589	1	0	0
T23	0	1	0	0
T25	906	0	0	0
T63	0	10	0	0
T66	0	10	0	0
T67	0	6	0	0
T108	0	5	0	0
T111	0	4	0	0
T113	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633692	21561	0	0
T1	354	2	0	0
T2	203	4	0	0
T3	222	1	0	0
T4	429	6	0	0
T5	373	7	0	0
T6	901	3	0	0
T7	974	7	0	0
T8	471	2	0	0
T9	190	1	0	0
T10	366	8	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633692	1118	0	0
T5	373	1	0	0
T6	901	0	0	0
T7	974	6	0	0
T8	471	0	0	0
T9	190	0	0	0
T10	366	0	0	0
T11	303	0	0	0
T12	471	0	0	0
T13	589	1	0	0
T23	0	1	0	0
T25	906	0	0	0
T63	0	10	0	0
T66	0	10	0	0
T67	0	6	0	0
T108	0	5	0	0
T111	0	4	0	0
T113	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14316	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	4	0	0
T6	7197	0	0	0
T7	7807	10	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1154	0	0
T7	7807	10	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T12	3781	0	0	0
T13	4727	0	0	0
T14	3703	0	0	0
T22	3516	0	0	0
T25	7228	0	0	0
T51	0	6	0	0
T63	0	11	0	0
T66	0	10	0	0
T67	0	7	0	0
T104	0	1	0	0
T108	0	6	0	0
T111	0	5	0	0
T113	0	7	0	0
T114	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14316	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	4	0	0
T6	7197	0	0	0
T7	7807	10	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1154	0	0
T7	7807	10	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T12	3781	0	0	0
T13	4727	0	0	0
T14	3703	0	0	0
T22	3516	0	0	0
T25	7228	0	0	0
T51	0	6	0	0
T63	0	11	0	0
T66	0	10	0	0
T67	0	7	0	0
T104	0	1	0	0
T108	0	6	0	0
T111	0	5	0	0
T113	0	7	0	0
T114	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14378	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	5	0	0
T6	7197	0	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	5	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1225	0	0
T5	2996	1	0	0
T6	7197	0	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T12	3781	0	0	0
T13	4727	1	0	0
T25	7228	0	0	0
T66	0	11	0	0
T67	0	7	0	0
T104	0	1	0	0
T108	0	8	0	0
T111	0	7	0	0
T113	0	9	0	0
T114	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14378	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	5	0	0
T6	7197	0	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	5	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1225	0	0
T5	2996	1	0	0
T6	7197	0	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T12	3781	0	0	0
T13	4727	1	0	0
T25	7228	0	0	0
T66	0	11	0	0
T67	0	7	0	0
T104	0	1	0	0
T108	0	8	0	0
T111	0	7	0	0
T113	0	9	0	0
T114	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14441	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	4	0	0
T6	7197	0	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	5	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1275	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T12	3781	0	0	0
T13	4727	0	0	0
T14	3703	0	0	0
T22	3516	0	0	0
T23	0	1	0	0
T25	7228	0	0	0
T63	0	13	0	0
T66	0	13	0	0
T67	0	9	0	0
T104	0	1	0	0
T108	0	8	0	0
T111	0	8	0	0
T113	0	11	0	0
T114	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	14441	0	0
T2	1631	3	0	0
T3	1788	0	0	0
T4	3444	4	0	0
T5	2996	4	0	0
T6	7197	0	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	7	0	0
T11	2431	4	0	0
T13	0	4	0	0
T14	0	8	0	0
T22	0	4	0	0
T23	0	5	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12928335	1275	0	0
T7	7807	11	0	0
T8	3767	0	0	0
T9	1537	0	0	0
T10	2947	0	0	0
T11	2431	0	0	0
T12	3781	0	0	0
T13	4727	0	0	0
T14	3703	0	0	0
T22	3516	0	0	0
T23	0	1	0	0
T25	7228	0	0	0
T63	0	13	0	0
T66	0	13	0	0
T67	0	9	0	0
T104	0	1	0	0
T108	0	8	0	0
T111	0	8	0	0
T113	0	11	0	0
T114	0	1	0	0