Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12205702	6762	0	0
alert_regwen_rd_A	12205702	5621	0	0
cpu_regwen_rd_A	12205702	5620	0	0
sw_rst_ctrl_n_0_rd_A	12205702	9543	0	0
sw_rst_ctrl_n_1_rd_A	12205702	9423	0	0
sw_rst_ctrl_n_2_rd_A	12205702	9535	0	0
sw_rst_ctrl_n_3_rd_A	12205702	9530	0	0
sw_rst_ctrl_n_4_rd_A	12205702	9321	0	0
sw_rst_ctrl_n_5_rd_A	12205702	9322	0	0
sw_rst_ctrl_n_6_rd_A	12205702	9514	0	0
sw_rst_ctrl_n_7_rd_A	12205702	9614	0	0
sw_rst_regwen_0_rd_A	12205702	5738	0	0
sw_rst_regwen_1_rd_A	12205702	5971	0	0
sw_rst_regwen_2_rd_A	12205702	6075	0	0
sw_rst_regwen_3_rd_A	12205702	5807	0	0
sw_rst_regwen_4_rd_A	12205702	6174	0	0
sw_rst_regwen_5_rd_A	12205702	6055	0	0
sw_rst_regwen_6_rd_A	12205702	5978	0	0
sw_rst_regwen_7_rd_A	12205702	6021	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	6762	0	0
T75	21966	4	0	0
T76	2786	9	0	0
T77	9875	373	0	0
T78	3004	12	0	0
T79	19041	3	0	0
T80	3853	95	0	0
T89	7112	327	0	0
T91	3640	715	0	0
T93	20440	4	0	0
T94	21779	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	5621	0	0
T20	5381	0	0	0
T21	3357	0	0	0
T26	50917	0	0	0
T36	4553	0	0	0
T54	46085	105	0	0
T55	2496	0	0	0
T85	0	78	0	0
T125	0	45	0	0
T126	0	40	0	0
T143	0	134	0	0
T144	0	495	0	0
T145	0	32	0	0
T146	0	58	0	0
T147	0	222	0	0
T148	0	426	0	0
T149	5822	0	0	0
T150	1538	0	0	0
T151	2277	0	0	0
T152	6702	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	5620	0	0
T20	5381	0	0	0
T21	3357	0	0	0
T26	50917	0	0	0
T36	4553	0	0	0
T54	46085	69	0	0
T55	2496	0	0	0
T85	0	81	0	0
T125	0	38	0	0
T126	0	44	0	0
T143	0	138	0	0
T144	0	523	0	0
T145	0	65	0	0
T146	0	59	0	0
T147	0	208	0	0
T148	0	429	0	0
T149	5822	0	0	0
T150	1538	0	0	0
T151	2277	0	0	0
T152	6702	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9543	0	0
T14	3161	39	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	219	0	0
T49	0	17	0	0
T54	0	98	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	68	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	11	0	0
T114	0	5	0	0
T125	0	66	0	0
T149	0	9	0	0
T153	0	109	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9423	0	0
T14	3161	19	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	201	0	0
T49	0	17	0	0
T54	0	91	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	51	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	18	0	0
T114	0	17	0	0
T125	0	30	0	0
T149	0	11	0	0
T153	0	127	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9535	0	0
T14	3161	21	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	210	0	0
T49	0	32	0	0
T54	0	87	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	83	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	15	0	0
T114	0	16	0	0
T125	0	35	0	0
T149	0	13	0	0
T153	0	95	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9530	0	0
T14	3161	44	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	238	0	0
T49	0	25	0	0
T54	0	61	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	86	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	10	0	0
T114	0	10	0	0
T125	0	38	0	0
T149	0	10	0	0
T153	0	104	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9321	0	0
T14	3161	43	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	215	0	0
T49	0	38	0	0
T54	0	80	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	68	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	9	0	0
T114	0	15	0	0
T125	0	66	0	0
T149	0	14	0	0
T153	0	113	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9322	0	0
T14	3161	41	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	214	0	0
T49	0	11	0	0
T54	0	87	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	77	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	9	0	0
T114	0	14	0	0
T125	0	26	0	0
T149	0	16	0	0
T153	0	128	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9514	0	0
T14	3161	22	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	238	0	0
T49	0	24	0	0
T54	0	76	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	93	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	7	0	0
T114	0	22	0	0
T125	0	30	0	0
T149	0	17	0	0
T153	0	99	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	9614	0	0
T14	3161	25	0	0
T15	3576	0	0	0
T22	3325	0	0	0
T23	4405	0	0	0
T24	2296	0	0	0
T38	0	200	0	0
T49	0	29	0	0
T54	0	96	0	0
T56	6282	0	0	0
T66	8203	0	0	0
T67	8325	81	0	0
T81	1497	0	0	0
T104	2678	0	0	0
T105	0	15	0	0
T114	0	14	0	0
T125	0	21	0	0
T149	0	19	0	0
T153	0	96	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	5738	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	32	0	0
T54	0	71	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	30	0	0
T85	0	81	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	5	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	8	0	0
T118	1219	0	0	0
T125	0	67	0	0
T126	0	42	0	0
T149	0	5	0	0
T153	0	33	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	5971	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	35	0	0
T54	0	99	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	17	0	0
T85	0	68	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	3	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	6	0	0
T118	1219	0	0	0
T125	0	19	0	0
T126	0	23	0	0
T149	0	2	0	0
T153	0	43	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	6075	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	25	0	0
T54	0	69	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	27	0	0
T85	0	83	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	1	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	2	0	0
T118	1219	0	0	0
T125	0	33	0	0
T126	0	30	0	0
T149	0	3	0	0
T153	0	22	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	5807	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	43	0	0
T54	0	82	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	18	0	0
T85	0	87	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	6	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	3	0	0
T118	1219	0	0	0
T125	0	43	0	0
T126	0	51	0	0
T149	0	11	0	0
T153	0	23	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	6174	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	21	0	0
T54	0	106	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	41	0	0
T85	0	55	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	7	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	5	0	0
T118	1219	0	0	0
T125	0	45	0	0
T126	0	36	0	0
T149	0	10	0	0
T153	0	19	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	6055	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	33	0	0
T54	0	82	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	36	0	0
T85	0	69	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	3	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	11	0	0
T118	1219	0	0	0
T125	0	28	0	0
T126	0	41	0	0
T149	0	15	0	0
T153	0	31	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	5978	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	35	0	0
T54	0	103	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	11	0	0
T85	0	65	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	14	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	8	0	0
T118	1219	0	0	0
T125	0	46	0	0
T126	0	46	0	0
T149	0	3	0	0
T153	0	21	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12205702	6021	0	0
T16	3218	0	0	0
T24	2296	0	0	0
T38	0	35	0	0
T54	0	104	0	0
T56	6282	0	0	0
T57	13727	0	0	0
T67	8325	11	0	0
T85	0	75	0	0
T103	6287	0	0	0
T104	2678	0	0	0
T105	0	4	0	0
T106	2608	0	0	0
T111	5982	0	0	0
T114	0	2	0	0
T118	1219	0	0	0
T125	0	49	0	0
T126	0	47	0	0
T149	0	3	0	0
T153	0	20	0	0