Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	650004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

390843

1

T2

137

T3

8

T4

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	555286	1			T1	1		T2	186		T4	63
values[0x0]	242563	1			T2	94		T3	16		T4	35
values[0x1]	242998	1			T2	99		T3	10		T4	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	545785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

495062

1

T1

1

T2

170

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4008	1			T2	2		T8	21		T79	1
valid_sources[0x01]	4286	1			T2	1		T8	8		T12	12
valid_sources[0x02]	5725	1			T2	1		T8	14		T25	1
valid_sources[0x03]	3207	1			T8	2		T13	2		T14	3
valid_sources[0x04]	3377	1			T4	2		T8	3		T14	1
valid_sources[0x05]	4545	1			T2	1		T4	1		T8	9
valid_sources[0x06]	3612	1			T8	17		T25	2		T76	3
valid_sources[0x07]	3760	1			T2	8		T4	1		T8	13
valid_sources[0x08]	3615	1			T2	2		T8	25		T14	5
valid_sources[0x09]	3518	1			T2	6		T4	1		T8	24
valid_sources[0x0a]	3375	1			T2	2		T8	7		T14	2
valid_sources[0x0b]	4060	1			T2	4		T8	35		T14	1
valid_sources[0x0c]	3936	1			T2	1		T8	11		T25	1
valid_sources[0x0d]	5496	1			T2	1		T8	5		T12	2
valid_sources[0x0e]	3460	1			T2	2		T76	1		T57	9
valid_sources[0x0f]	3741	1			T2	2		T8	18		T14	2
valid_sources[0x10]	3788	1			T2	3		T8	2		T10	1
valid_sources[0x11]	3520	1			T2	3		T4	1		T8	7
valid_sources[0x12]	3698	1			T4	1		T8	4		T79	1
valid_sources[0x13]	3586	1			T8	14		T77	11		T44	25
valid_sources[0x14]	3972	1			T4	1		T14	3		T79	1
valid_sources[0x15]	3476	1			T2	3		T4	1		T8	3
valid_sources[0x16]	3495	1			T2	2		T4	1		T8	20
valid_sources[0x17]	3816	1			T1	1		T2	2		T8	14
valid_sources[0x18]	4918	1			T2	1		T4	1		T8	1
valid_sources[0x19]	3806	1			T2	1		T8	1		T12	1
valid_sources[0x1a]	4409	1			T8	18		T14	1		T79	1
valid_sources[0x1b]	3757	1			T2	3		T4	3		T8	12
valid_sources[0x1c]	3674	1			T2	1		T4	1		T14	2
valid_sources[0x1d]	3376	1			T2	3		T8	4		T13	8
valid_sources[0x1e]	3860	1			T2	1		T8	11		T12	16
valid_sources[0x1f]	4455	1			T2	1		T8	6		T14	4
valid_sources[0x20]	3666	1			T2	3		T8	15		T14	2
valid_sources[0x21]	3711	1			T4	3		T8	12		T14	1
valid_sources[0x22]	4147	1			T2	2		T4	1		T8	13
valid_sources[0x23]	4047	1			T8	20		T14	1		T25	1
valid_sources[0x24]	4168	1			T2	3		T4	1		T8	13
valid_sources[0x25]	3493	1			T8	7		T14	1		T25	3
valid_sources[0x26]	3342	1			T2	1		T8	4		T14	3
valid_sources[0x27]	3909	1			T2	2		T8	9		T79	1
valid_sources[0x28]	3800	1			T2	1		T4	1		T8	13
valid_sources[0x29]	7521	1			T4	2		T8	11		T14	2
valid_sources[0x2a]	3970	1			T14	3		T79	1		T77	5
valid_sources[0x2b]	3287	1			T2	1		T8	10		T13	6
valid_sources[0x2c]	3809	1			T2	1		T8	10		T14	5
valid_sources[0x2d]	3851	1			T2	4		T8	7		T12	3
valid_sources[0x2e]	3685	1			T2	5		T8	6		T13	1
valid_sources[0x2f]	3561	1			T8	12		T14	3		T25	3
valid_sources[0x30]	3446	1			T2	1		T4	1		T8	12
valid_sources[0x31]	3540	1			T3	26		T4	1		T8	20
valid_sources[0x32]	3576	1			T2	3		T8	13		T76	3
valid_sources[0x33]	3513	1			T2	1		T8	4		T14	3
valid_sources[0x34]	3701	1			T2	1		T13	10		T14	8
valid_sources[0x35]	4200	1			T2	3		T8	18		T14	2
valid_sources[0x36]	3539	1			T2	2		T8	23		T12	5
valid_sources[0x37]	3709	1			T2	3		T8	3		T12	2
valid_sources[0x38]	3494	1			T2	2		T25	1		T79	3
valid_sources[0x39]	3981	1			T4	2		T8	12		T14	2
valid_sources[0x3a]	4004	1			T8	26		T10	1		T14	3
valid_sources[0x3b]	3655	1			T2	1		T4	1		T8	17
valid_sources[0x3c]	3218	1			T2	1		T11	1		T12	1
valid_sources[0x3d]	4111	1			T8	12		T12	12		T13	21
valid_sources[0x3e]	4014	1			T2	1		T4	1		T14	2
valid_sources[0x3f]	3538	1			T2	2		T8	5		T12	3
valid_sources[0x40]	4669	1			T2	2		T8	5		T12	1
valid_sources[0x41]	3492	1			T2	2		T8	11		T12	3
valid_sources[0x42]	4331	1			T2	1		T4	1		T8	14
valid_sources[0x43]	3744	1			T2	1		T8	18		T12	9
valid_sources[0x44]	6114	1			T4	1		T8	6		T14	2
valid_sources[0x45]	3795	1			T4	3		T8	21		T12	5
valid_sources[0x46]	3532	1			T8	6		T14	2		T25	1
valid_sources[0x47]	3965	1			T2	2		T4	1		T8	2
valid_sources[0x48]	3980	1			T8	13		T10	1		T14	1
valid_sources[0x49]	5460	1			T2	1		T8	20		T14	3
valid_sources[0x4a]	4336	1			T8	5		T14	4		T79	1
valid_sources[0x4b]	3425	1			T2	3		T4	1		T8	13
valid_sources[0x4c]	3425	1			T2	2		T8	15		T14	2
valid_sources[0x4d]	3607	1			T2	2		T4	1		T8	2
valid_sources[0x4e]	3925	1			T2	1		T4	1		T8	24
valid_sources[0x4f]	3312	1			T2	2		T4	1		T8	7
valid_sources[0x50]	3620	1			T2	1		T8	7		T57	4
valid_sources[0x51]	4137	1			T8	33		T14	2		T79	1
valid_sources[0x52]	3581	1			T2	2		T8	20		T76	4
valid_sources[0x53]	3592	1			T2	2		T8	20		T13	10
valid_sources[0x54]	3794	1			T2	1		T8	15		T14	5
valid_sources[0x55]	3449	1			T2	2		T72	1		T79	1
valid_sources[0x56]	3505	1			T2	5		T8	19		T14	4
valid_sources[0x57]	4634	1			T2	1		T8	10		T14	1
valid_sources[0x58]	3830	1			T4	2		T8	1		T14	2
valid_sources[0x59]	3210	1			T2	1		T4	1		T8	3
valid_sources[0x5a]	3018	1			T2	1		T4	3		T8	7
valid_sources[0x5b]	4326	1			T2	1		T8	16		T12	5
valid_sources[0x5c]	6708	1			T2	1		T8	32		T76	3
valid_sources[0x5d]	3795	1			T2	3		T8	7		T14	3
valid_sources[0x5e]	4637	1			T2	1		T14	5		T76	2
valid_sources[0x5f]	5188	1			T2	2		T4	2		T8	10
valid_sources[0x60]	4110	1			T2	1		T8	5		T14	1
valid_sources[0x61]	4578	1			T76	1		T77	6		T44	10
valid_sources[0x62]	4625	1			T2	1		T8	8		T14	2
valid_sources[0x63]	3340	1			T2	2		T14	4		T16	1
valid_sources[0x64]	4381	1			T8	56		T13	2		T79	1
valid_sources[0x65]	4208	1			T2	2		T8	12		T13	4
valid_sources[0x66]	4706	1			T4	1		T8	9		T12	3
valid_sources[0x67]	3774	1			T2	1		T14	1		T25	1
valid_sources[0x68]	3772	1			T2	1		T8	5		T14	3
valid_sources[0x69]	3402	1			T2	1		T4	1		T8	10
valid_sources[0x6a]	5624	1			T2	1		T8	10		T14	1
valid_sources[0x6b]	4762	1			T2	1		T8	12		T14	2
valid_sources[0x6c]	3637	1			T2	1		T4	2		T8	14
valid_sources[0x6d]	3764	1			T8	5		T13	3		T14	3
valid_sources[0x6e]	3549	1			T2	1		T8	24		T76	3
valid_sources[0x6f]	3861	1			T8	15		T76	6		T77	10
valid_sources[0x70]	5936	1			T2	1		T8	22		T10	1
valid_sources[0x71]	3533	1			T4	1		T79	1		T77	12
valid_sources[0x72]	4354	1			T2	4		T4	1		T8	39
valid_sources[0x73]	5213	1			T8	1		T14	5		T72	5
valid_sources[0x74]	3982	1			T2	4		T14	2		T77	5
valid_sources[0x75]	3597	1			T2	3		T8	30		T14	3
valid_sources[0x76]	3203	1			T2	3		T8	7		T14	1
valid_sources[0x77]	4706	1			T2	4		T4	1		T8	9
valid_sources[0x78]	3716	1			T2	1		T4	1		T8	12
valid_sources[0x79]	3662	1			T2	1		T8	5		T10	1
valid_sources[0x7a]	3526	1			T8	11		T79	1		T77	1
valid_sources[0x7b]	3957	1			T2	2		T8	4		T12	3
valid_sources[0x7c]	4802	1			T6	1096		T12	4		T14	1
valid_sources[0x7d]	3988	1			T2	1		T8	1		T14	1
valid_sources[0x7e]	3815	1			T8	17		T12	9		T14	1
valid_sources[0x7f]	6550	1			T2	3		T8	6		T12	2
valid_sources[0x80]	3539	1			T14	1		T77	25		T44	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

260868

1

T2

90

T4

32

T5

46

values[0x0]

all_enables

biggest_size

84889

1

T2

34

T3

6

T4

9

values[0x1]

all_enables

biggest_size

45086

1

T2

13

T3

2

T4

5