Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_root_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_clean_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_out_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1381020	1348700	0	0
selKnown1	184000	151680	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381020	1348700	0	0
T1	158	94	0	0
T2	350	286	0	0
T3	64	0	0	0
T4	449	385	0	0
T5	347	283	0	0
T6	149	85	0	0
T7	662	598	0	0
T8	3250	3186	0	0
T9	6082	6018	0	0
T10	17344	17280	0	0
T11	0	84	0	0
T12	0	243	0	0
T15	0	81	0	0
T16	0	1	0	0
T17	0	2	0	0
T75	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	184000	151680	0	0
T2	128	64	0	0
T3	64	0	0	0
T4	64	0	0	0
T5	128	64	0	0
T6	64	0	0	0
T7	64	0	0	0
T8	704	640	0	0
T9	64	0	0	0
T10	64	0	0	0
T11	64	0	0	0
T12	0	64	0	0
T14	0	64	0	0
T24	0	64	0	0
T25	0	64	0	0
T65	0	64	0	0
T76	0	64	0	0
T77	0	576	0	0

Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23320	22815	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23320	22815	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23385	22880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385	22880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24346	23841	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24346	23841	0	0
T1	2	1	0	0
T2	7	6	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	6	5	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24385	23880	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24385	23880	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	10	9	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24427	23922	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24427	23922	0	0
T1	2	1	0	0
T2	7	6	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	11	10	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24467	23962	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24467	23962	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	9	8	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24528	24023	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24528	24023	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	11	10	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23320	22815	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23320	22815	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24589	24084	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24589	24084	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	14	13	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24641	24136	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24641	24136	0	0
T1	2	1	0	0
T2	7	6	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	15	14	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24694	24189	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694	24189	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	17	16	0	0
T7	10	9	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23435	22930	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23435	22930	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	1	0	0	0
T4	8	7	0	0
T5	6	5	0	0
T6	1	0	0	0
T7	11	10	0	0
T8	56	55	0	0
T9	106	105	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7686	7181	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7686	7181	0	0
T1	17	16	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	10	9	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	11	0	0
T15	0	9	0	0
T16	0	1	0	0
T17	0	2	0	0
T75	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	10018	9513	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	10018	9513	0	0
T1	17	16	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	11	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T8,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9582	9077	0	0
selKnown1	2875	2370	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9582	9077	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	10	9	0	0
T8	20	19	0	0
T9	28	27	0	0
T10	271	270	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2370	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	2	1	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	11	10	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	9	0	0