Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T79
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T57
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T57,T58
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T57
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T57,T58
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T14
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T57,T58
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13608511	14764	0	0
gen_assertions[0].RstEnOn_A	13608511	1165	0	0
gen_assertions[0].RstNOff_A	13608511	14764	0	0
gen_assertions[0].RstNOn_A	13608511	1165	0	0
gen_assertions[1].RstEnOff_A	54433705	13444	0	0
gen_assertions[1].RstEnOn_A	54433705	1122	0	0
gen_assertions[1].RstNOff_A	54433705	13444	0	0
gen_assertions[1].RstNOn_A	54433705	1122	0	0
gen_assertions[2].RstEnOff_A	27217788	13486	0	0
gen_assertions[2].RstEnOn_A	27217788	1094	0	0
gen_assertions[2].RstNOff_A	27217788	13486	0	0
gen_assertions[2].RstNOn_A	27217788	1094	0	0
gen_assertions[3].RstEnOff_A	27217398	13526	0	0
gen_assertions[3].RstEnOn_A	27217398	1127	0	0
gen_assertions[3].RstNOff_A	27217398	13526	0	0
gen_assertions[3].RstNOn_A	27217398	1127	0	0
gen_assertions[4].RstEnOff_A	1719405	23011	0	0
gen_assertions[4].RstEnOn_A	1719405	1197	0	0
gen_assertions[4].RstNOff_A	1719405	23011	0	0
gen_assertions[4].RstNOn_A	1719405	1197	0	0
gen_assertions[5].RstEnOff_A	13608511	15007	0	0
gen_assertions[5].RstEnOn_A	13608511	1245	0	0
gen_assertions[5].RstNOff_A	13608511	15007	0	0
gen_assertions[5].RstNOn_A	13608511	1245	0	0
gen_assertions[6].RstEnOff_A	13608511	15059	0	0
gen_assertions[6].RstEnOn_A	13608511	1293	0	0
gen_assertions[6].RstNOff_A	13608511	15059	0	0
gen_assertions[6].RstNOn_A	13608511	1293	0	0
gen_assertions[7].RstEnOff_A	13608511	15112	0	0
gen_assertions[7].RstEnOn_A	13608511	1347	0	0
gen_assertions[7].RstNOff_A	13608511	15112	0	0
gen_assertions[7].RstNOn_A	13608511	1347	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	14764	0	0
T2	4881	5	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	5	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	5	0	0
T13	0	12	0	0
T14	0	4	0	0
T24	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1165	0	0
T2	4881	1	0	0
T3	1638	0	0	0
T4	3243	1	0	0
T5	4169	0	0	0
T6	3677	5	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T39	0	7	0	0
T57	0	1	0	0
T58	0	2	0	0
T65	0	1	0	0
T79	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	14764	0	0
T2	4881	5	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	5	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	5	0	0
T13	0	12	0	0
T14	0	4	0	0
T24	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1165	0	0
T2	4881	1	0	0
T3	1638	0	0	0
T4	3243	1	0	0
T5	4169	0	0	0
T6	3677	5	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T39	0	7	0	0
T57	0	1	0	0
T58	0	2	0	0
T65	0	1	0	0
T79	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54433705	13444	0	0
T2	19532	3	0	0
T3	6560	0	0	0
T4	12977	7	0	0
T5	16668	4	0	0
T6	14712	9	0	0
T7	28737	0	0	0
T8	87141	33	0	0
T9	121127	75	0	0
T10	792755	0	0	0
T11	15611	0	0	0
T12	0	3	0	0
T13	0	10	0	0
T14	0	3	0	0
T24	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54433705	1122	0	0
T6	14712	9	0	0
T7	28737	0	0	0
T8	87141	0	0	0
T9	121127	0	0	0
T10	792755	0	0	0
T11	15611	0	0	0
T12	18623	1	0	0
T13	16236	0	0	0
T14	19304	0	0	0
T15	28912	0	0	0
T39	0	7	0	0
T57	0	1	0	0
T58	0	6	0	0
T79	0	1	0	0
T80	0	9	0	0
T81	0	3	0	0
T82	0	2	0	0
T83	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54433705	13444	0	0
T2	19532	3	0	0
T3	6560	0	0	0
T4	12977	7	0	0
T5	16668	4	0	0
T6	14712	9	0	0
T7	28737	0	0	0
T8	87141	33	0	0
T9	121127	75	0	0
T10	792755	0	0	0
T11	15611	0	0	0
T12	0	3	0	0
T13	0	10	0	0
T14	0	3	0	0
T24	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54433705	1122	0	0
T6	14712	9	0	0
T7	28737	0	0	0
T8	87141	0	0	0
T9	121127	0	0	0
T10	792755	0	0	0
T11	15611	0	0	0
T12	18623	1	0	0
T13	16236	0	0	0
T14	19304	0	0	0
T15	28912	0	0	0
T39	0	7	0	0
T57	0	1	0	0
T58	0	6	0	0
T79	0	1	0	0
T80	0	9	0	0
T81	0	3	0	0
T82	0	2	0	0
T83	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217788	13486	0	0
T2	9765	4	0	0
T3	3279	0	0	0
T4	6487	7	0	0
T5	8334	4	0	0
T6	7355	10	0	0
T7	14374	0	0	0
T8	43571	33	0	0
T9	60553	75	0	0
T10	396421	0	0	0
T11	7806	0	0	0
T12	0	2	0	0
T13	0	10	0	0
T14	0	3	0	0
T24	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217788	1094	0	0
T2	9765	1	0	0
T3	3279	0	0	0
T4	6487	0	0	0
T5	8334	0	0	0
T6	7355	10	0	0
T7	14374	0	0	0
T8	43571	0	0	0
T9	60553	0	0	0
T10	396421	0	0	0
T11	7806	0	0	0
T39	0	10	0	0
T57	0	2	0	0
T58	0	7	0	0
T80	0	9	0	0
T82	0	5	0	0
T84	0	9	0	0
T85	0	3	0	0
T86	0	46	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217788	13486	0	0
T2	9765	4	0	0
T3	3279	0	0	0
T4	6487	7	0	0
T5	8334	4	0	0
T6	7355	10	0	0
T7	14374	0	0	0
T8	43571	33	0	0
T9	60553	75	0	0
T10	396421	0	0	0
T11	7806	0	0	0
T12	0	2	0	0
T13	0	10	0	0
T14	0	3	0	0
T24	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217788	1094	0	0
T2	9765	1	0	0
T3	3279	0	0	0
T4	6487	0	0	0
T5	8334	0	0	0
T6	7355	10	0	0
T7	14374	0	0	0
T8	43571	0	0	0
T9	60553	0	0	0
T10	396421	0	0	0
T11	7806	0	0	0
T39	0	10	0	0
T57	0	2	0	0
T58	0	7	0	0
T80	0	9	0	0
T82	0	5	0	0
T84	0	9	0	0
T85	0	3	0	0
T86	0	46	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217398	13526	0	0
T2	9762	3	0	0
T3	3279	0	0	0
T4	6488	7	0	0
T5	8336	4	0	0
T6	7354	8	0	0
T7	14368	0	0	0
T8	43580	33	0	0
T9	60578	75	0	0
T10	396423	0	0	0
T11	7806	0	0	0
T12	0	2	0	0
T13	0	10	0	0
T14	0	3	0	0
T24	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217398	1127	0	0
T6	7354	8	0	0
T7	14368	0	0	0
T8	43580	0	0	0
T9	60578	0	0	0
T10	396423	0	0	0
T11	7806	0	0	0
T12	9313	0	0	0
T13	8119	0	0	0
T14	9651	0	0	0
T15	14453	0	0	0
T39	0	10	0	0
T57	0	4	0	0
T58	0	9	0	0
T80	0	10	0	0
T82	0	6	0	0
T84	0	11	0	0
T85	0	5	0	0
T86	0	52	0	0
T87	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217398	13526	0	0
T2	9762	3	0	0
T3	3279	0	0	0
T4	6488	7	0	0
T5	8336	4	0	0
T6	7354	8	0	0
T7	14368	0	0	0
T8	43580	33	0	0
T9	60578	75	0	0
T10	396423	0	0	0
T11	7806	0	0	0
T12	0	2	0	0
T13	0	10	0	0
T14	0	3	0	0
T24	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27217398	1127	0	0
T6	7354	8	0	0
T7	14368	0	0	0
T8	43580	0	0	0
T9	60578	0	0	0
T10	396423	0	0	0
T11	7806	0	0	0
T12	9313	0	0	0
T13	8119	0	0	0
T14	9651	0	0	0
T15	14453	0	0	0
T39	0	10	0	0
T57	0	4	0	0
T58	0	9	0	0
T80	0	10	0	0
T82	0	6	0	0
T84	0	11	0	0
T85	0	5	0	0
T86	0	52	0	0
T87	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719405	23011	0	0
T1	665	2	0	0
T2	609	6	0	0
T3	203	1	0	0
T4	405	8	0	0
T5	521	6	0	0
T6	459	11	0	0
T7	900	3	0	0
T8	2794	55	0	0
T9	3800	80	0	0
T10	24897	271	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719405	1197	0	0
T6	459	10	0	0
T7	900	0	0	0
T8	2794	0	0	0
T9	3800	0	0	0
T10	24897	0	0	0
T11	486	0	0	0
T12	580	1	0	0
T13	506	0	0	0
T14	602	0	0	0
T15	906	0	0	0
T39	0	10	0	0
T57	0	5	0	0
T58	0	10	0	0
T80	0	13	0	0
T82	0	7	0	0
T84	0	9	0	0
T88	0	1	0	0
T89	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719405	23011	0	0
T1	665	2	0	0
T2	609	6	0	0
T3	203	1	0	0
T4	405	8	0	0
T5	521	6	0	0
T6	459	11	0	0
T7	900	3	0	0
T8	2794	55	0	0
T9	3800	80	0	0
T10	24897	271	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719405	1197	0	0
T6	459	10	0	0
T7	900	0	0	0
T8	2794	0	0	0
T9	3800	0	0	0
T10	24897	0	0	0
T11	486	0	0	0
T12	580	1	0	0
T13	506	0	0	0
T14	602	0	0	0
T15	906	0	0	0
T39	0	10	0	0
T57	0	5	0	0
T58	0	10	0	0
T80	0	13	0	0
T82	0	7	0	0
T84	0	9	0	0
T88	0	1	0	0
T89	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	15007	0	0
T2	4881	4	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	13	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	4	0	0
T24	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1245	0	0
T6	3677	13	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	4655	0	0	0
T13	4058	0	0	0
T14	4824	0	0	0
T15	7227	0	0	0
T39	0	9	0	0
T57	0	6	0	0
T58	0	11	0	0
T80	0	12	0	0
T82	0	7	0	0
T84	0	12	0	0
T85	0	7	0	0
T86	0	46	0	0
T90	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	15007	0	0
T2	4881	4	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	13	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	4	0	0
T24	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1245	0	0
T6	3677	13	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	4655	0	0	0
T13	4058	0	0	0
T14	4824	0	0	0
T15	7227	0	0	0
T39	0	9	0	0
T57	0	6	0	0
T58	0	11	0	0
T80	0	12	0	0
T82	0	7	0	0
T84	0	12	0	0
T85	0	7	0	0
T86	0	46	0	0
T90	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	15059	0	0
T2	4881	5	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	14	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	5	0	0
T24	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1293	0	0
T2	4881	1	0	0
T3	1638	0	0	0
T4	3243	0	0	0
T5	4169	0	0	0
T6	3677	14	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T14	0	1	0	0
T39	0	14	0	0
T57	0	7	0	0
T58	0	11	0	0
T76	0	1	0	0
T80	0	12	0	0
T82	0	7	0	0
T84	0	14	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	15059	0	0
T2	4881	5	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	14	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	5	0	0
T24	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1293	0	0
T2	4881	1	0	0
T3	1638	0	0	0
T4	3243	0	0	0
T5	4169	0	0	0
T6	3677	14	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T14	0	1	0	0
T39	0	14	0	0
T57	0	7	0	0
T58	0	11	0	0
T76	0	1	0	0
T80	0	12	0	0
T82	0	7	0	0
T84	0	14	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	15112	0	0
T2	4881	4	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	16	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	4	0	0
T24	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1347	0	0
T6	3677	16	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	4655	0	0	0
T13	4058	0	0	0
T14	4824	0	0	0
T15	7227	0	0	0
T39	0	13	0	0
T43	0	1	0	0
T57	0	7	0	0
T58	0	12	0	0
T80	0	13	0	0
T82	0	7	0	0
T84	0	15	0	0
T85	0	10	0	0
T90	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	15112	0	0
T2	4881	4	0	0
T3	1638	0	0	0
T4	3243	7	0	0
T5	4169	4	0	0
T6	3677	16	0	0
T7	7183	0	0	0
T8	21789	36	0	0
T9	30289	78	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	4	0	0
T24	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13608511	1347	0	0
T6	3677	16	0	0
T7	7183	0	0	0
T8	21789	0	0	0
T9	30289	0	0	0
T10	198229	0	0	0
T11	3902	0	0	0
T12	4655	0	0	0
T13	4058	0	0	0
T14	4824	0	0	0
T15	7227	0	0	0
T39	0	13	0	0
T43	0	1	0	0
T57	0	7	0	0
T58	0	12	0	0
T80	0	13	0	0
T82	0	7	0	0
T84	0	15	0	0
T85	0	10	0	0
T90	0	1	0	0