Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12840424	6511	0	0
alert_regwen_rd_A	12840424	5427	0	0
cpu_regwen_rd_A	12840424	5238	0	0
sw_rst_ctrl_n_0_rd_A	12840424	9389	0	0
sw_rst_ctrl_n_1_rd_A	12840424	9731	0	0
sw_rst_ctrl_n_2_rd_A	12840424	9265	0	0
sw_rst_ctrl_n_3_rd_A	12840424	9118	0	0
sw_rst_ctrl_n_4_rd_A	12840424	9081	0	0
sw_rst_ctrl_n_5_rd_A	12840424	9284	0	0
sw_rst_ctrl_n_6_rd_A	12840424	9054	0	0
sw_rst_ctrl_n_7_rd_A	12840424	9265	0	0
sw_rst_regwen_0_rd_A	12840424	5725	0	0
sw_rst_regwen_1_rd_A	12840424	5662	0	0
sw_rst_regwen_2_rd_A	12840424	5714	0	0
sw_rst_regwen_3_rd_A	12840424	5652	0	0
sw_rst_regwen_4_rd_A	12840424	5827	0	0
sw_rst_regwen_5_rd_A	12840424	5820	0	0
sw_rst_regwen_6_rd_A	12840424	5517	0	0
sw_rst_regwen_7_rd_A	12840424	5495	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	6511	0	0
T61	4761	137	0	0
T68	2162	83	0	0
T69	2502	5	0	0
T70	11245	1	0	0
T71	22304	2	0	0
T92	2880	12	0	0
T93	3716	59	0	0
T94	5501	134	0	0
T95	8313	327	0	0
T98	3080	15	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5427	0	0
T18	4042	0	0	0
T37	39798	62	0	0
T38	2027	0	0	0
T39	8409	0	0	0
T40	2258	0	0	0
T41	2339	0	0	0
T42	1676	0	0	0
T43	2615	0	0	0
T80	3261	0	0	0
T101	0	53	0	0
T102	0	45	0	0
T104	1762	0	0	0
T106	0	63	0	0
T109	0	88	0	0
T112	0	21	0	0
T114	0	79	0	0
T134	0	48	0	0
T135	0	107	0	0
T136	0	104	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5238	0	0
T18	4042	0	0	0
T37	39798	40	0	0
T38	2027	0	0	0
T39	8409	0	0	0
T40	2258	0	0	0
T41	2339	0	0	0
T42	1676	0	0	0
T43	2615	0	0	0
T80	3261	0	0	0
T101	0	47	0	0
T102	0	36	0	0
T104	1762	0	0	0
T106	0	80	0	0
T109	0	117	0	0
T112	0	21	0	0
T114	0	87	0	0
T134	0	44	0	0
T135	0	124	0	0
T136	0	74	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9389	0	0
T4	2758	29	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	30	0	0
T38	0	9	0	0
T65	0	10	0	0
T85	0	99	0	0
T87	0	163	0	0
T89	0	9	0	0
T101	0	57	0	0
T102	0	42	0	0
T137	0	16	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9731	0	0
T4	2758	20	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	80	0	0
T65	0	6	0	0
T85	0	101	0	0
T87	0	160	0	0
T89	0	15	0	0
T101	0	44	0	0
T102	0	62	0	0
T137	0	19	0	0
T138	0	6	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9265	0	0
T4	2758	28	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	57	0	0
T38	0	6	0	0
T65	0	16	0	0
T85	0	121	0	0
T87	0	177	0	0
T89	0	12	0	0
T101	0	64	0	0
T102	0	46	0	0
T138	0	4	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9118	0	0
T4	2758	19	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	54	0	0
T38	0	6	0	0
T65	0	26	0	0
T85	0	101	0	0
T87	0	140	0	0
T89	0	9	0	0
T101	0	55	0	0
T102	0	55	0	0
T137	0	17	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9081	0	0
T4	2758	21	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	65	0	0
T38	0	13	0	0
T65	0	14	0	0
T85	0	61	0	0
T87	0	150	0	0
T89	0	5	0	0
T101	0	50	0	0
T102	0	39	0	0
T138	0	9	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9284	0	0
T4	2758	29	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	59	0	0
T38	0	6	0	0
T65	0	16	0	0
T85	0	79	0	0
T87	0	171	0	0
T101	0	46	0	0
T102	0	51	0	0
T137	0	23	0	0
T139	0	55	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9054	0	0
T4	2758	23	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	49	0	0
T38	0	8	0	0
T65	0	18	0	0
T85	0	86	0	0
T87	0	161	0	0
T89	0	6	0	0
T101	0	56	0	0
T102	0	47	0	0
T138	0	8	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	9265	0	0
T4	2758	18	0	0
T5	3927	0	0	0
T6	3610	0	0	0
T7	6743	0	0	0
T8	17113	0	0	0
T9	27049	0	0	0
T10	192694	0	0	0
T11	3787	0	0	0
T12	4462	0	0	0
T15	6548	0	0	0
T37	0	60	0	0
T38	0	6	0	0
T65	0	11	0	0
T85	0	77	0	0
T87	0	195	0	0
T89	0	6	0	0
T101	0	45	0	0
T102	0	48	0	0
T138	0	3	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5725	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	52	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	11	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	14	0	0
T87	0	39	0	0
T101	0	50	0	0
T102	0	39	0	0
T106	0	80	0	0
T109	0	102	0	0
T134	0	43	0	0
T137	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5662	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	69	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	12	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	13	0	0
T87	0	50	0	0
T89	0	19	0	0
T101	0	30	0	0
T102	0	49	0	0
T106	0	59	0	0
T109	0	89	0	0
T137	0	2	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5714	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	67	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	8	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	11	0	0
T87	0	25	0	0
T89	0	2	0	0
T101	0	64	0	0
T102	0	35	0	0
T106	0	79	0	0
T109	0	71	0	0
T137	0	1	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5652	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	60	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	4	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	27	0	0
T87	0	24	0	0
T89	0	1	0	0
T101	0	45	0	0
T102	0	38	0	0
T106	0	86	0	0
T109	0	84	0	0
T137	0	1	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5827	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	50	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	6	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	23	0	0
T87	0	30	0	0
T89	0	2	0	0
T101	0	54	0	0
T102	0	37	0	0
T106	0	94	0	0
T109	0	95	0	0
T137	0	13	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5820	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	42	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	13	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	20	0	0
T87	0	26	0	0
T89	0	4	0	0
T101	0	51	0	0
T102	0	35	0	0
T106	0	79	0	0
T109	0	104	0	0
T137	0	6	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5517	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	52	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	12	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	12	0	0
T87	0	14	0	0
T101	0	62	0	0
T102	0	33	0	0
T106	0	61	0	0
T109	0	76	0	0
T134	0	37	0	0
T137	0	10	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12840424	5495	0	0
T26	27360	0	0	0
T36	32578	0	0	0
T37	39798	39	0	0
T44	27297	0	0	0
T57	6474	0	0	0
T58	8020	0	0	0
T65	5942	4	0	0
T76	2372	0	0	0
T77	13951	0	0	0
T78	6996	0	0	0
T85	0	18	0	0
T87	0	36	0	0
T101	0	58	0	0
T102	0	43	0	0
T106	0	60	0	0
T109	0	99	0	0
T134	0	59	0	0
T137	0	6	0	0