Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	604363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363107

1

T1

2

T3

67

T5

122

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	516255	1			T2	1		T3	99		T4	1
values[0x0]	225450	1			T1	2		T3	50		T5	101
values[0x1]	225765	1			T1	5		T3	54		T5	92

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	507077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460393

1

T1

2

T3

82

T5

157

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3532	1			T3	1		T6	5		T7	4
valid_sources[0x01]	3369	1			T3	1		T6	6		T7	3
valid_sources[0x02]	3648	1			T6	4		T7	3		T8	11
valid_sources[0x03]	3567	1			T3	2		T6	4		T7	5
valid_sources[0x04]	3295	1			T3	1		T5	2		T6	2
valid_sources[0x05]	4694	1			T6	6		T7	4		T8	10
valid_sources[0x06]	3192	1			T3	2		T5	9		T6	5
valid_sources[0x07]	3038	1			T5	3		T6	2		T7	1
valid_sources[0x08]	3668	1			T3	1		T5	1		T6	13
valid_sources[0x09]	4173	1			T1	2		T6	4		T7	6
valid_sources[0x0a]	3296	1			T3	2		T5	2		T6	6
valid_sources[0x0b]	3100	1			T5	1		T6	2		T7	5
valid_sources[0x0c]	4680	1			T5	1		T6	2		T7	9
valid_sources[0x0d]	3812	1			T6	4		T7	6		T8	18
valid_sources[0x0e]	3457	1			T3	1		T5	3		T6	4
valid_sources[0x0f]	2890	1			T5	1		T6	3		T7	6
valid_sources[0x10]	3030	1			T6	4		T7	1		T9	39
valid_sources[0x11]	8599	1			T3	3		T5	1		T6	6
valid_sources[0x12]	4651	1			T3	2		T6	6		T7	4
valid_sources[0x13]	3755	1			T3	2		T5	2		T6	5
valid_sources[0x14]	3112	1			T6	5		T7	2		T8	4
valid_sources[0x15]	3889	1			T5	1		T6	3		T7	4
valid_sources[0x16]	2811	1			T3	1		T5	1		T6	4
valid_sources[0x17]	4092	1			T3	1		T5	3		T6	5
valid_sources[0x18]	3229	1			T3	1		T5	1		T6	8
valid_sources[0x19]	3231	1			T3	1		T5	2		T6	3
valid_sources[0x1a]	3557	1			T5	6		T6	4		T7	5
valid_sources[0x1b]	3055	1			T6	4		T7	4		T8	23
valid_sources[0x1c]	5053	1			T6	5		T7	1		T8	1
valid_sources[0x1d]	3486	1			T5	2		T6	4		T7	8
valid_sources[0x1e]	3425	1			T3	2		T6	5		T7	7
valid_sources[0x1f]	3077	1			T3	1		T6	2		T7	6
valid_sources[0x20]	3203	1			T6	4		T7	3		T8	4
valid_sources[0x21]	3500	1			T3	1		T6	1		T7	2
valid_sources[0x22]	4237	1			T3	2		T6	3		T7	2
valid_sources[0x23]	3457	1			T5	3		T6	7		T7	2
valid_sources[0x24]	3928	1			T3	3		T6	4		T7	9
valid_sources[0x25]	3443	1			T3	1		T5	1		T6	4
valid_sources[0x26]	3311	1			T6	4		T7	1		T8	8
valid_sources[0x27]	3182	1			T3	1		T6	3		T7	1
valid_sources[0x28]	5207	1			T6	4		T7	1		T8	8
valid_sources[0x29]	3771	1			T6	5		T8	7		T9	106
valid_sources[0x2a]	4689	1			T3	1		T6	5		T7	1
valid_sources[0x2b]	4489	1			T3	2		T6	5		T7	4
valid_sources[0x2c]	2739	1			T3	3		T5	4		T6	1
valid_sources[0x2d]	4082	1			T3	2		T5	1		T6	5
valid_sources[0x2e]	3358	1			T3	1		T6	1		T7	7
valid_sources[0x2f]	4384	1			T5	4		T6	4		T7	1
valid_sources[0x30]	3731	1			T5	5		T6	2		T10	4
valid_sources[0x31]	5256	1			T3	1		T6	1		T7	9
valid_sources[0x32]	2964	1			T3	1		T5	2		T6	4
valid_sources[0x33]	3030	1			T5	6		T6	6		T7	3
valid_sources[0x34]	3791	1			T3	1		T5	3		T6	3
valid_sources[0x35]	3601	1			T5	2		T6	2		T7	5
valid_sources[0x36]	3726	1			T3	1		T5	2		T6	2
valid_sources[0x37]	3346	1			T3	2		T5	3		T6	4
valid_sources[0x38]	4236	1			T3	2		T6	1		T7	1
valid_sources[0x39]	3065	1			T3	1		T6	6		T7	1
valid_sources[0x3a]	6198	1			T3	1		T5	7		T6	2
valid_sources[0x3b]	3369	1			T3	1		T5	3		T6	2
valid_sources[0x3c]	4863	1			T3	1		T5	1		T6	5
valid_sources[0x3d]	4567	1			T3	2		T6	7		T7	2
valid_sources[0x3e]	3211	1			T3	1		T5	1		T6	4
valid_sources[0x3f]	3235	1			T5	8		T6	4		T7	5
valid_sources[0x40]	6775	1			T3	2		T6	2		T7	6
valid_sources[0x41]	3204	1			T5	1		T6	5		T7	1
valid_sources[0x42]	3206	1			T5	5		T6	2		T7	5
valid_sources[0x43]	3112	1			T3	3		T5	5		T6	6
valid_sources[0x44]	2904	1			T3	1		T5	1		T6	4
valid_sources[0x45]	3449	1			T6	1		T7	6		T8	7
valid_sources[0x46]	3518	1			T5	1		T6	4		T7	2
valid_sources[0x47]	3429	1			T3	1		T7	4		T24	1
valid_sources[0x48]	3013	1			T3	1		T6	1		T7	2
valid_sources[0x49]	4204	1			T5	2		T6	10		T7	4
valid_sources[0x4a]	3246	1			T5	3		T6	1		T7	9
valid_sources[0x4b]	2928	1			T3	1		T5	2		T6	3
valid_sources[0x4c]	3167	1			T6	7		T7	8		T8	12
valid_sources[0x4d]	2912	1			T3	1		T6	11		T7	1
valid_sources[0x4e]	3986	1			T6	7		T7	10		T8	5
valid_sources[0x4f]	3136	1			T5	1		T6	4		T7	12
valid_sources[0x50]	7465	1			T3	1		T6	3		T7	1
valid_sources[0x51]	3554	1			T3	1		T6	3		T7	5
valid_sources[0x52]	6920	1			T5	1		T6	5		T7	13
valid_sources[0x53]	3700	1			T3	5		T5	3		T6	3
valid_sources[0x54]	3158	1			T3	1		T5	2		T6	7
valid_sources[0x55]	3495	1			T6	2		T7	3		T8	14
valid_sources[0x56]	3631	1			T5	1		T6	2		T7	9
valid_sources[0x57]	3176	1			T3	1		T6	1		T7	2
valid_sources[0x58]	4584	1			T6	4		T7	3		T8	13
valid_sources[0x59]	3134	1			T5	2		T6	3		T7	5
valid_sources[0x5a]	3690	1			T3	2		T5	2		T6	7
valid_sources[0x5b]	3252	1			T5	2		T6	4		T7	3
valid_sources[0x5c]	3149	1			T6	3		T7	2		T8	8
valid_sources[0x5d]	2907	1			T3	2		T5	3		T6	5
valid_sources[0x5e]	3829	1			T5	1		T6	6		T7	10
valid_sources[0x5f]	3298	1			T3	1		T5	7		T6	2
valid_sources[0x60]	3274	1			T3	2		T5	2		T6	6
valid_sources[0x61]	2953	1			T3	1		T6	3		T7	4
valid_sources[0x62]	4221	1			T3	1		T6	3		T7	5
valid_sources[0x63]	3031	1			T3	2		T5	3		T6	2
valid_sources[0x64]	3988	1			T3	2		T5	1		T6	3
valid_sources[0x65]	3383	1			T6	3		T7	1		T8	26
valid_sources[0x66]	3479	1			T6	4		T7	6		T8	6
valid_sources[0x67]	3878	1			T6	6		T7	5		T8	6
valid_sources[0x68]	3058	1			T3	1		T6	6		T7	5
valid_sources[0x69]	3301	1			T3	2		T5	4		T6	3
valid_sources[0x6a]	3763	1			T3	1		T6	1		T7	4
valid_sources[0x6b]	3650	1			T3	3		T5	1		T6	4
valid_sources[0x6c]	3764	1			T3	1		T5	4		T6	2
valid_sources[0x6d]	3831	1			T6	3		T7	9		T8	12
valid_sources[0x6e]	3585	1			T5	1		T6	4		T7	6
valid_sources[0x6f]	3798	1			T3	2		T6	4		T7	5
valid_sources[0x70]	3366	1			T5	6		T6	3		T7	3
valid_sources[0x71]	3539	1			T6	3		T7	1		T8	7
valid_sources[0x72]	3084	1			T3	1		T6	2		T7	2
valid_sources[0x73]	3301	1			T3	1		T5	3		T6	2
valid_sources[0x74]	5428	1			T3	2		T6	12		T7	1
valid_sources[0x75]	2850	1			T6	2		T8	7		T10	1
valid_sources[0x76]	3120	1			T3	1		T5	1		T6	2
valid_sources[0x77]	3346	1			T3	2		T6	10		T7	7
valid_sources[0x78]	3510	1			T3	2		T6	5		T7	3
valid_sources[0x79]	3451	1			T3	3		T5	5		T6	2
valid_sources[0x7a]	4493	1			T3	3		T6	1		T7	1
valid_sources[0x7b]	3270	1			T3	2		T5	1		T6	4
valid_sources[0x7c]	6518	1			T2	1		T3	1		T5	1
valid_sources[0x7d]	5069	1			T6	5		T7	1		T8	10
valid_sources[0x7e]	5594	1			T6	7		T7	6		T8	13
valid_sources[0x7f]	3598	1			T3	1		T5	1		T6	3
valid_sources[0x80]	3795	1			T3	1		T6	4		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241707

1

T3

44

T5

75

T6

274

values[0x0]

all_enables

biggest_size

78991

1

T1

1

T3

15

T5

30

values[0x1]

all_enables

biggest_size

42409

1

T1

1

T3

8

T5

17