Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T4,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11753907	12811	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11753907	118334	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11753907	6762985	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11753907	188357	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11753907	12811	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11753907	118334	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11753907	6762985	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11753907	188357	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	12811	0	0
T3	2960	11	0	0
T4	3865	0	0	0
T5	4543	4	0	0
T6	3401	0	0	0
T7	3369	0	0	0
T8	28511	28	0	0
T9	27041	78	0	0
T10	2616	4	0	0
T11	5893	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T23	0	4	0	0
T24	0	4	0	0
T25	2042	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	118334	0	0
T3	2960	99	0	0
T4	3865	0	0	0
T5	4543	37	0	0
T6	3401	0	0	0
T7	3369	0	0	0
T8	28511	254	0	0
T9	27041	742	0	0
T10	2616	38	0	0
T11	5893	38	0	0
T12	0	37	0	0
T13	0	37	0	0
T23	0	37	0	0
T24	0	36	0	0
T25	2042	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	6762985	0	0
T1	1464	819	0	0
T2	4338	606	0	0
T3	2960	2155	0	0
T4	3865	871	0	0
T5	4543	3567	0	0
T6	3401	2826	0	0
T7	3369	2732	0	0
T8	28511	19105	0	0
T9	27041	9116	0	0
T10	2616	1638	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	188357	0	0
T3	2960	164	0	0
T4	3865	0	0	0
T5	4543	65	0	0
T6	3401	0	0	0
T7	3369	0	0	0
T8	28511	400	0	0
T9	27041	1144	0	0
T10	2616	52	0	0
T11	5893	53	0	0
T12	0	51	0	0
T13	0	53	0	0
T23	0	60	0	0
T24	0	54	0	0
T25	2042	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	12811	0	0
T3	2960	11	0	0
T4	3865	0	0	0
T5	4543	4	0	0
T6	3401	0	0	0
T7	3369	0	0	0
T8	28511	28	0	0
T9	27041	78	0	0
T10	2616	4	0	0
T11	5893	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T23	0	4	0	0
T24	0	4	0	0
T25	2042	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	118334	0	0
T3	2960	99	0	0
T4	3865	0	0	0
T5	4543	37	0	0
T6	3401	0	0	0
T7	3369	0	0	0
T8	28511	254	0	0
T9	27041	742	0	0
T10	2616	38	0	0
T11	5893	38	0	0
T12	0	37	0	0
T13	0	37	0	0
T23	0	37	0	0
T24	0	36	0	0
T25	2042	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	6762985	0	0
T1	1464	819	0	0
T2	4338	606	0	0
T3	2960	2155	0	0
T4	3865	871	0	0
T5	4543	3567	0	0
T6	3401	2826	0	0
T7	3369	2732	0	0
T8	28511	19105	0	0
T9	27041	9116	0	0
T10	2616	1638	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	188357	0	0
T3	2960	164	0	0
T4	3865	0	0	0
T5	4543	65	0	0
T6	3401	0	0	0
T7	3369	0	0	0
T8	28511	400	0	0
T9	27041	1144	0	0
T10	2616	52	0	0
T11	5893	53	0	0
T12	0	51	0	0
T13	0	53	0	0
T23	0	60	0	0
T24	0	54	0	0
T25	2042	0	0	0