Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T5 T8 T10 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T5 T8 T10 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T10
0	1	Covered	T8,T10,T11
1	0	Covered	T8,T13,T49

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T5,T8,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55120231	9172	0	0
CascadeEffAonToRstPorAboveRise_A	55120231	9172	0	0
CascadeEffAonToRstPorIoAboveFall_A	52913567	9172	0	0
CascadeEffAonToRstPorIoAboveRise_A	52913567	9172	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26457537	9172	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26457537	9172	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13228444	9172	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13228444	9172	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26457722	9172	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26457722	9172	0	0
CascadeLcToLcAboveFall_A	55120231	21983	0	0
CascadeLcToLcAboveRise_A	55120231	21983	0	0
CascadeLcToLcAonAboveFall_A	1669982	21983	0	0
CascadeLcToLcAonAboveRise_A	1669982	21983	0	0
CascadeLcToLcShadowedAboveFall_A	55120231	21983	0	0
CascadeLcToLcShadowedAboveRise_A	55120231	21983	0	0
CascadePorToAonAboveFall_A	1669982	7426	0	0
CascadeSysToSysAboveFall_A	55120231	21983	0	0
CascadeSysToSysAboveRise_A	55120231	21983	0	0
ScanRstToAonRise_A	1669982	192	0	0
StablePorToAonRise_A	1669982	9172	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11753907	21983	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11753907	21983	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11753907	21983	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11753907	21983	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13228444	21983	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13228444	21983	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11753907	21983	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11753907	21983	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11753907	21983	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11753907	21983	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	9172	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	1	0	0
T4	16586	2	0	0
T5	20315	2	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	20	0	0
T9	126236	28	0	0
T10	11913	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	9172	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	1	0	0
T4	16586	2	0	0
T5	20315	2	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	20	0	0
T9	126236	28	0	0
T10	11913	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52913567	9172	0	0
T1	5932	1	0	0
T2	18102	2	0	0
T3	14359	1	0	0
T4	15923	2	0	0
T5	19506	2	0	0
T6	13971	1	0	0
T7	13556	1	0	0
T8	132243	20	0	0
T9	121155	28	0	0
T10	11433	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52913567	9172	0	0
T1	5932	1	0	0
T2	18102	2	0	0
T3	14359	1	0	0
T4	15923	2	0	0
T5	19506	2	0	0
T6	13971	1	0	0
T7	13556	1	0	0
T8	132243	20	0	0
T9	121155	28	0	0
T10	11433	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457537	9172	0	0
T1	2966	1	0	0
T2	9050	2	0	0
T3	7178	1	0	0
T4	7961	2	0	0
T5	9753	2	0	0
T6	6985	1	0	0
T7	6778	1	0	0
T8	66127	20	0	0
T9	60583	28	0	0
T10	5718	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457537	9172	0	0
T1	2966	1	0	0
T2	9050	2	0	0
T3	7178	1	0	0
T4	7961	2	0	0
T5	9753	2	0	0
T6	6985	1	0	0
T7	6778	1	0	0
T8	66127	20	0	0
T9	60583	28	0	0
T10	5718	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	9172	0	0
T1	1481	1	0	0
T2	4523	2	0	0
T3	3589	1	0	0
T4	3980	2	0	0
T5	4874	2	0	0
T6	3492	1	0	0
T7	3388	1	0	0
T8	33061	20	0	0
T9	30294	28	0	0
T10	2857	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	9172	0	0
T1	1481	1	0	0
T2	4523	2	0	0
T3	3589	1	0	0
T4	3980	2	0	0
T5	4874	2	0	0
T6	3492	1	0	0
T7	3388	1	0	0
T8	33061	20	0	0
T9	30294	28	0	0
T10	2857	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457722	9172	0	0
T1	2966	1	0	0
T2	9050	2	0	0
T3	7179	1	0	0
T4	7961	2	0	0
T5	9748	2	0	0
T6	6985	1	0	0
T7	6778	1	0	0
T8	66121	20	0	0
T9	60596	28	0	0
T10	5715	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457722	9172	0	0
T1	2966	1	0	0
T2	9050	2	0	0
T3	7179	1	0	0
T4	7961	2	0	0
T5	9748	2	0	0
T6	6985	1	0	0
T7	6778	1	0	0
T8	66121	20	0	0
T9	60596	28	0	0
T10	5715	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	21983	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	12	0	0
T4	16586	2	0	0
T5	20315	6	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	48	0	0
T9	126236	106	0	0
T10	11913	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	21983	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	12	0	0
T4	16586	2	0	0
T5	20315	6	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	48	0	0
T9	126236	106	0	0
T10	11913	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	21983	0	0
T1	184	1	0	0
T2	564	2	0	0
T3	448	12	0	0
T4	496	2	0	0
T5	608	6	0	0
T6	435	1	0	0
T7	423	1	0	0
T8	4202	48	0	0
T9	3801	106	0	0
T10	356	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	21983	0	0
T1	184	1	0	0
T2	564	2	0	0
T3	448	12	0	0
T4	496	2	0	0
T5	608	6	0	0
T6	435	1	0	0
T7	423	1	0	0
T8	4202	48	0	0
T9	3801	106	0	0
T10	356	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	21983	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	12	0	0
T4	16586	2	0	0
T5	20315	6	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	48	0	0
T9	126236	106	0	0
T10	11913	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	21983	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	12	0	0
T4	16586	2	0	0
T5	20315	6	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	48	0	0
T9	126236	106	0	0
T10	11913	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	7426	0	0
T1	184	1	0	0
T2	564	18	0	0
T3	448	1	0	0
T4	496	13	0	0
T5	608	1	0	0
T6	435	1	0	0
T7	423	1	0	0
T8	4202	13	0	0
T9	3801	28	0	0
T10	356	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	21983	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	12	0	0
T4	16586	2	0	0
T5	20315	6	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	48	0	0
T9	126236	106	0	0
T10	11913	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55120231	21983	0	0
T1	6180	1	0	0
T2	18856	2	0	0
T3	14959	12	0	0
T4	16586	2	0	0
T5	20315	6	0	0
T6	14554	1	0	0
T7	14122	1	0	0
T8	137746	48	0	0
T9	126236	106	0	0
T10	11913	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	192	0	0
T15	245	0	0	0
T16	484	0	0	0
T17	368	0	0	0
T49	9407	4	0	0
T50	514	0	0	0
T51	906	0	0	0
T52	0	1	0	0
T59	910	0	0	0
T66	182	0	0	0
T83	560	0	0	0
T92	0	1	0	0
T94	0	1	0	0
T96	0	3	0	0
T98	0	3	0	0
T103	251	0	0	0
T104	0	2	0	0
T105	0	1	0	0
T110	0	2	0	0
T111	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	9172	0	0
T1	184	1	0	0
T2	564	2	0	0
T3	448	1	0	0
T4	496	2	0	0
T5	608	2	0	0
T6	435	1	0	0
T7	423	1	0	0
T8	4202	20	0	0
T9	3801	28	0	0
T10	356	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	21983	0	0
T1	1481	1	0	0
T2	4523	2	0	0
T3	3589	12	0	0
T4	3980	2	0	0
T5	4874	6	0	0
T6	3492	1	0	0
T7	3388	1	0	0
T8	33061	48	0	0
T9	30294	106	0	0
T10	2857	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	21983	0	0
T1	1481	1	0	0
T2	4523	2	0	0
T3	3589	12	0	0
T4	3980	2	0	0
T5	4874	6	0	0
T6	3492	1	0	0
T7	3388	1	0	0
T8	33061	48	0	0
T9	30294	106	0	0
T10	2857	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11753907	21983	0	0
T1	1464	1	0	0
T2	4338	2	0	0
T3	2960	12	0	0
T4	3865	2	0	0
T5	4543	6	0	0
T6	3401	1	0	0
T7	3369	1	0	0
T8	28511	48	0	0
T9	27041	106	0	0
T10	2616	6	0	0