Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T49
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T49
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T49
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13228444	13704	0	0
gen_assertions[0].RstEnOn_A	13228444	1066	0	0
gen_assertions[0].RstNOff_A	13228444	13704	0	0
gen_assertions[0].RstNOn_A	13228444	1066	0	0
gen_assertions[1].RstEnOff_A	52913567	12486	0	0
gen_assertions[1].RstEnOn_A	52913567	1059	0	0
gen_assertions[1].RstNOff_A	52913567	12486	0	0
gen_assertions[1].RstNOn_A	52913567	1059	0	0
gen_assertions[2].RstEnOff_A	26457537	12488	0	0
gen_assertions[2].RstEnOn_A	26457537	1007	0	0
gen_assertions[2].RstNOff_A	26457537	12488	0	0
gen_assertions[2].RstNOn_A	26457537	1007	0	0
gen_assertions[3].RstEnOff_A	26457722	12564	0	0
gen_assertions[3].RstEnOn_A	26457722	1085	0	0
gen_assertions[3].RstNOff_A	26457722	12564	0	0
gen_assertions[3].RstNOn_A	26457722	1085	0	0
gen_assertions[4].RstEnOff_A	1669982	21666	0	0
gen_assertions[4].RstEnOn_A	1669982	1122	0	0
gen_assertions[4].RstNOff_A	1669982	21666	0	0
gen_assertions[4].RstNOn_A	1669982	1122	0	0
gen_assertions[5].RstEnOff_A	13228444	13954	0	0
gen_assertions[5].RstEnOn_A	13228444	1177	0	0
gen_assertions[5].RstNOff_A	13228444	13954	0	0
gen_assertions[5].RstNOn_A	13228444	1177	0	0
gen_assertions[6].RstEnOff_A	13228444	13993	0	0
gen_assertions[6].RstEnOn_A	13228444	1227	0	0
gen_assertions[6].RstNOff_A	13228444	13993	0	0
gen_assertions[6].RstNOn_A	13228444	1227	0	0
gen_assertions[7].RstEnOff_A	13228444	14052	0	0
gen_assertions[7].RstEnOn_A	13228444	1282	0	0
gen_assertions[7].RstNOff_A	13228444	14052	0	0
gen_assertions[7].RstNOn_A	13228444	1282	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	13704	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	5	0	0
T6	3492	7	0	0
T7	3388	7	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	4	0	0
T11	6085	5	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1066	0	0
T5	4874	1	0	0
T6	3492	7	0	0
T7	3388	7	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	0	0	0
T11	6085	1	0	0
T12	2420	0	0	0
T14	7195	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	2131	0	0	0
T49	0	8	0	0
T53	0	8	0	0
T85	0	5	0	0
T86	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	13704	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	5	0	0
T6	3492	7	0	0
T7	3388	7	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	4	0	0
T11	6085	5	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1066	0	0
T5	4874	1	0	0
T6	3492	7	0	0
T7	3388	7	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	0	0	0
T11	6085	1	0	0
T12	2420	0	0	0
T14	7195	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	2131	0	0	0
T49	0	8	0	0
T53	0	8	0	0
T85	0	5	0	0
T86	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52913567	12486	0	0
T3	14359	11	0	0
T4	15923	0	0	0
T5	19506	5	0	0
T6	13971	6	0	0
T7	13556	8	0	0
T8	132243	26	0	0
T9	121155	73	0	0
T10	11433	3	0	0
T11	24347	2	0	0
T12	0	2	0	0
T13	0	5	0	0
T25	8532	0	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52913567	1059	0	0
T5	19506	1	0	0
T6	13971	6	0	0
T7	13556	8	0	0
T8	132243	0	0	0
T9	121155	0	0	0
T10	11433	0	0	0
T11	24347	0	0	0
T12	9680	0	0	0
T13	0	1	0	0
T14	28798	0	0	0
T24	0	2	0	0
T25	8532	0	0	0
T45	0	6	0	0
T49	0	7	0	0
T53	0	8	0	0
T85	0	3	0	0
T87	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52913567	12486	0	0
T3	14359	11	0	0
T4	15923	0	0	0
T5	19506	5	0	0
T6	13971	6	0	0
T7	13556	8	0	0
T8	132243	26	0	0
T9	121155	73	0	0
T10	11433	3	0	0
T11	24347	2	0	0
T12	0	2	0	0
T13	0	5	0	0
T25	8532	0	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52913567	1059	0	0
T5	19506	1	0	0
T6	13971	6	0	0
T7	13556	8	0	0
T8	132243	0	0	0
T9	121155	0	0	0
T10	11433	0	0	0
T11	24347	0	0	0
T12	9680	0	0	0
T13	0	1	0	0
T14	28798	0	0	0
T24	0	2	0	0
T25	8532	0	0	0
T45	0	6	0	0
T49	0	7	0	0
T53	0	8	0	0
T85	0	3	0	0
T87	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457537	12488	0	0
T3	7178	11	0	0
T4	7961	0	0	0
T5	9753	4	0	0
T6	6985	10	0	0
T7	6778	7	0	0
T8	66127	26	0	0
T9	60583	73	0	0
T10	5718	3	0	0
T11	12173	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T25	4265	0	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457537	1007	0	0
T6	6985	10	0	0
T7	6778	7	0	0
T8	66127	0	0	0
T9	60583	0	0	0
T10	5718	0	0	0
T11	12173	0	0	0
T12	4838	0	0	0
T13	8995	0	0	0
T14	14387	0	0	0
T25	4265	0	0	0
T47	0	10	0	0
T49	0	4	0	0
T53	0	7	0	0
T85	0	1	0	0
T87	0	6	0	0
T88	0	6	0	0
T89	0	2	0	0
T90	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457537	12488	0	0
T3	7178	11	0	0
T4	7961	0	0	0
T5	9753	4	0	0
T6	6985	10	0	0
T7	6778	7	0	0
T8	66127	26	0	0
T9	60583	73	0	0
T10	5718	3	0	0
T11	12173	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T25	4265	0	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457537	1007	0	0
T6	6985	10	0	0
T7	6778	7	0	0
T8	66127	0	0	0
T9	60583	0	0	0
T10	5718	0	0	0
T11	12173	0	0	0
T12	4838	0	0	0
T13	8995	0	0	0
T14	14387	0	0	0
T25	4265	0	0	0
T47	0	10	0	0
T49	0	4	0	0
T53	0	7	0	0
T85	0	1	0	0
T87	0	6	0	0
T88	0	6	0	0
T89	0	2	0	0
T90	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457722	12564	0	0
T3	7179	11	0	0
T4	7961	0	0	0
T5	9748	4	0	0
T6	6985	11	0	0
T7	6778	8	0	0
T8	66121	26	0	0
T9	60596	73	0	0
T10	5715	4	0	0
T11	12175	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T25	4265	0	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457722	1085	0	0
T6	6985	11	0	0
T7	6778	8	0	0
T8	66121	0	0	0
T9	60596	0	0	0
T10	5715	1	0	0
T11	12175	0	0	0
T12	4838	0	0	0
T13	8996	0	0	0
T14	14393	0	0	0
T25	4265	0	0	0
T47	0	8	0	0
T49	0	8	0	0
T53	0	9	0	0
T87	0	9	0	0
T88	0	8	0	0
T89	0	4	0	0
T91	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457722	12564	0	0
T3	7179	11	0	0
T4	7961	0	0	0
T5	9748	4	0	0
T6	6985	11	0	0
T7	6778	8	0	0
T8	66121	26	0	0
T9	60596	73	0	0
T10	5715	4	0	0
T11	12175	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T25	4265	0	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26457722	1085	0	0
T6	6985	11	0	0
T7	6778	8	0	0
T8	66121	0	0	0
T9	60596	0	0	0
T10	5715	1	0	0
T11	12175	0	0	0
T12	4838	0	0	0
T13	8996	0	0	0
T14	14393	0	0	0
T25	4265	0	0	0
T47	0	8	0	0
T49	0	8	0	0
T53	0	9	0	0
T87	0	9	0	0
T88	0	8	0	0
T89	0	4	0	0
T91	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	21666	0	0
T1	184	1	0	0
T2	564	2	0	0
T3	448	12	0	0
T4	496	2	0	0
T5	608	6	0	0
T6	435	14	0	0
T7	423	11	0	0
T8	4202	48	0	0
T9	3801	80	0	0
T10	356	7	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	1122	0	0
T6	435	13	0	0
T7	423	10	0	0
T8	4202	0	0	0
T9	3801	0	0	0
T10	356	1	0	0
T11	759	0	0	0
T12	302	0	0	0
T13	562	0	0	0
T14	902	0	0	0
T25	266	0	0	0
T47	0	11	0	0
T49	0	10	0	0
T53	0	10	0	0
T87	0	8	0	0
T88	0	7	0	0
T91	0	1	0	0
T92	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	21666	0	0
T1	184	1	0	0
T2	564	2	0	0
T3	448	12	0	0
T4	496	2	0	0
T5	608	6	0	0
T6	435	14	0	0
T7	423	11	0	0
T8	4202	48	0	0
T9	3801	80	0	0
T10	356	7	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1669982	1122	0	0
T6	435	13	0	0
T7	423	10	0	0
T8	4202	0	0	0
T9	3801	0	0	0
T10	356	1	0	0
T11	759	0	0	0
T12	302	0	0	0
T13	562	0	0	0
T14	902	0	0	0
T25	266	0	0	0
T47	0	11	0	0
T49	0	10	0	0
T53	0	10	0	0
T87	0	8	0	0
T88	0	7	0	0
T91	0	1	0	0
T92	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	13954	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	4	0	0
T6	3492	11	0	0
T7	3388	10	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	4	0	0
T11	6085	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1177	0	0
T6	3492	11	0	0
T7	3388	10	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	0	0	0
T11	6085	0	0	0
T12	2420	0	0	0
T13	4496	0	0	0
T14	7195	0	0	0
T25	2131	0	0	0
T47	0	12	0	0
T49	0	9	0	0
T53	0	9	0	0
T87	0	10	0	0
T88	0	9	0	0
T89	0	5	0	0
T90	0	1	0	0
T93	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	13954	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	4	0	0
T6	3492	11	0	0
T7	3388	10	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	4	0	0
T11	6085	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1177	0	0
T6	3492	11	0	0
T7	3388	10	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	0	0	0
T11	6085	0	0	0
T12	2420	0	0	0
T13	4496	0	0	0
T14	7195	0	0	0
T25	2131	0	0	0
T47	0	12	0	0
T49	0	9	0	0
T53	0	9	0	0
T87	0	10	0	0
T88	0	9	0	0
T89	0	5	0	0
T90	0	1	0	0
T93	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	13993	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	5	0	0
T6	3492	13	0	0
T7	3388	14	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	5	0	0
T11	6085	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1227	0	0
T5	4874	1	0	0
T6	3492	13	0	0
T7	3388	14	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	1	0	0
T11	6085	0	0	0
T12	2420	0	0	0
T14	7195	0	0	0
T23	0	1	0	0
T25	2131	0	0	0
T49	0	9	0	0
T52	0	1	0	0
T53	0	14	0	0
T87	0	12	0	0
T92	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	13993	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	5	0	0
T6	3492	13	0	0
T7	3388	14	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	5	0	0
T11	6085	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1227	0	0
T5	4874	1	0	0
T6	3492	13	0	0
T7	3388	14	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	1	0	0
T11	6085	0	0	0
T12	2420	0	0	0
T14	7195	0	0	0
T23	0	1	0	0
T25	2131	0	0	0
T49	0	9	0	0
T52	0	1	0	0
T53	0	14	0	0
T87	0	12	0	0
T92	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	14052	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	4	0	0
T6	3492	15	0	0
T7	3388	11	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	4	0	0
T11	6085	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1282	0	0
T6	3492	15	0	0
T7	3388	11	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	0	0	0
T11	6085	0	0	0
T12	2420	0	0	0
T13	4496	0	0	0
T14	7195	0	0	0
T25	2131	0	0	0
T47	0	12	0	0
T49	0	10	0	0
T52	0	1	0	0
T53	0	14	0	0
T87	0	12	0	0
T88	0	11	0	0
T89	0	7	0	0
T92	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	14052	0	0
T3	3589	11	0	0
T4	3980	0	0	0
T5	4874	4	0	0
T6	3492	15	0	0
T7	3388	11	0	0
T8	33061	28	0	0
T9	30294	78	0	0
T10	2857	4	0	0
T11	6085	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T25	2131	0	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13228444	1282	0	0
T6	3492	15	0	0
T7	3388	11	0	0
T8	33061	0	0	0
T9	30294	0	0	0
T10	2857	0	0	0
T11	6085	0	0	0
T12	2420	0	0	0
T13	4496	0	0	0
T14	7195	0	0	0
T25	2131	0	0	0
T47	0	12	0	0
T49	0	10	0	0
T52	0	1	0	0
T53	0	14	0	0
T87	0	12	0	0
T88	0	11	0	0
T89	0	7	0	0
T92	0	1	0	0