Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_daon_por.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 893001058 472634553 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 893001058 472634553 0 0
T1 100082 55779 0 0
T2 305430 47782 0 0
T3 242300 158524 0 0
T4 268680 68067 0 0
T5 329090 245502 0 0
T6 235748 187373 0 0
T7 228752 181458 0 0
T8 2231858 1333479 0 0
T9 2044896 673333 0 0
T10 192936 114293 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55120231 32546366 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55120231 32546366 0 0
T1 6180 3482 0 0
T2 18856 3424 0 0
T3 14959 12273 0 0
T4 16586 4830 0 0
T5 20315 16072 0 0
T6 14554 11844 0 0
T7 14122 11451 0 0
T8 137746 90801 0 0
T9 126236 51171 0 0
T10 11913 7807 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 52913567 31243092 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 52913567 31243092 0 0
T1 5932 3343 0 0
T2 18102 3288 0 0
T3 14359 11782 0 0
T4 15923 4637 0 0
T5 19506 15433 0 0
T6 13971 11370 0 0
T7 13556 10993 0 0
T8 132243 87164 0 0
T9 121155 49107 0 0
T10 11433 7490 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457537 15617742 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457537 15617742 0 0
T1 2966 1671 0 0
T2 9050 1643 0 0
T3 7178 5890 0 0
T4 7961 2317 0 0
T5 9753 7715 0 0
T6 6985 5685 0 0
T7 6778 5496 0 0
T8 66127 43574 0 0
T9 60583 24578 0 0
T10 5718 3746 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 7805314 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 7805314 0 0
T1 1481 835 0 0
T2 4523 820 0 0
T3 3589 2945 0 0
T4 3980 1158 0 0
T5 4874 3856 0 0
T6 3492 2842 0 0
T7 3388 2747 0 0
T8 33061 21778 0 0
T9 30294 12259 0 0
T10 2857 1872 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457722 15617850 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457722 15617850 0 0
T1 2966 1671 0 0
T2 9050 1643 0 0
T3 7179 5890 0 0
T4 7961 2317 0 0
T5 9748 7711 0 0
T6 6985 5685 0 0
T7 6778 5496 0 0
T8 66121 43571 0 0
T9 60596 24586 0 0
T10 5715 3743 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55120231 29017282 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55120231 29017282 0 0
T1 6180 3478 0 0
T2 18856 3413 0 0
T3 14959 9313 0 0
T4 16586 4819 0 0
T5 20315 15095 0 0
T6 14554 11838 0 0
T7 14122 11445 0 0
T8 137746 81323 0 0
T9 126236 41156 0 0
T10 11913 6998 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55120231 28270714 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55120231 28270714 0 0
T1 6180 3411 0 0
T2 18856 2513 0 0
T3 14959 9159 0 0
T4 16586 3620 0 0
T5 20315 14929 0 0
T6 14554 11772 0 0
T7 14122 11378 0 0
T8 137746 79754 0 0
T9 126236 38576 0 0
T10 11913 6833 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55120231 29017350 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55120231 29017350 0 0
T1 6180 3478 0 0
T2 18856 3413 0 0
T3 14959 9313 0 0
T4 16586 4819 0 0
T5 20315 15095 0 0
T6 14554 11838 0 0
T7 14122 11445 0 0
T8 137746 81323 0 0
T9 126236 41156 0 0
T10 11913 6998 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55120231 28271057 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55120231 28271057 0 0
T1 6180 3411 0 0
T2 18856 2513 0 0
T3 14959 9159 0 0
T4 16586 3620 0 0
T5 20315 14929 0 0
T6 14554 11772 0 0
T7 14122 11378 0 0
T8 137746 79754 0 0
T9 126236 38572 0 0
T10 11913 6833 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1669982 860396 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1669982 860396 0 0
T1 184 103 0 0
T2 564 100 0 0
T3 448 267 0 0
T4 496 142 0 0
T5 608 446 0 0
T6 435 354 0 0
T7 423 342 0 0
T8 4202 2451 0 0
T9 3801 1122 0 0
T10 356 203 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 52913567 27855824 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 52913567 27855824 0 0
T1 5932 3339 0 0
T2 18102 3277 0 0
T3 14359 8942 0 0
T4 15923 4626 0 0
T5 19506 14495 0 0
T6 13971 11364 0 0
T7 13556 10987 0 0
T8 132243 78066 0 0
T9 121155 39426 0 0
T10 11433 6714 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 52913567 27140084 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 52913567 27140084 0 0
T1 5932 3275 0 0
T2 18102 2413 0 0
T3 14359 8790 0 0
T4 15923 3474 0 0
T5 19506 14335 0 0
T6 13971 11300 0 0
T7 13556 10923 0 0
T8 132243 76562 0 0
T9 121155 37026 0 0
T10 11433 6554 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457537 13918106 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457537 13918106 0 0
T1 2966 1669 0 0
T2 9050 1637 0 0
T3 7178 4465 0 0
T4 7961 2313 0 0
T5 9753 7245 0 0
T6 6985 5682 0 0
T7 6778 5493 0 0
T8 66127 39012 0 0
T9 60583 19677 0 0
T10 5718 3356 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457537 13559715 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457537 13559715 0 0
T1 2966 1637 0 0
T2 9050 1205 0 0
T3 7178 4389 0 0
T4 7961 1737 0 0
T5 9753 7165 0 0
T6 6985 5650 0 0
T7 6778 5461 0 0
T8 66127 38260 0 0
T9 60583 18467 0 0
T10 5718 3276 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6931391 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6931391 0 0
T1 1481 833 0 0
T2 4523 816 0 0
T3 3589 2215 0 0
T4 3980 1154 0 0
T5 4874 3614 0 0
T6 3492 2840 0 0
T7 3388 2745 0 0
T8 33061 19448 0 0
T9 30294 9704 0 0
T10 2857 1670 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6752307 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6752307 0 0
T1 1481 817 0 0
T2 4523 600 0 0
T3 3589 2177 0 0
T4 3980 866 0 0
T5 4874 3574 0 0
T6 3492 2824 0 0
T7 3388 2729 0 0
T8 33061 19072 0 0
T9 30294 9100 0 0
T10 2857 1630 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6931391 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6931391 0 0
T1 1481 833 0 0
T2 4523 816 0 0
T3 3589 2215 0 0
T4 3980 1154 0 0
T5 4874 3614 0 0
T6 3492 2840 0 0
T7 3388 2745 0 0
T8 33061 19448 0 0
T9 30294 9704 0 0
T10 2857 1670 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6752307 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6752307 0 0
T1 1481 817 0 0
T2 4523 600 0 0
T3 3589 2177 0 0
T4 3980 866 0 0
T5 4874 3574 0 0
T6 3492 2824 0 0
T7 3388 2729 0 0
T8 33061 19072 0 0
T9 30294 9100 0 0
T10 2857 1630 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457722 13918221 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457722 13918221 0 0
T1 2966 1669 0 0
T2 9050 1637 0 0
T3 7179 4465 0 0
T4 7961 2313 0 0
T5 9748 7241 0 0
T6 6985 5682 0 0
T7 6778 5493 0 0
T8 66121 39009 0 0
T9 60596 19690 0 0
T10 5715 3353 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457722 13560146 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457722 13560146 0 0
T1 2966 1637 0 0
T2 9050 1205 0 0
T3 7179 4389 0 0
T4 7961 1737 0 0
T5 9748 7161 0 0
T6 6985 5650 0 0
T7 6778 5461 0 0
T8 66121 38257 0 0
T9 60596 18504 0 0
T10 5715 3273 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 55120231 27981048 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55120231 27981048 0 0
T1 6180 3411 0 0
T2 18856 2513 0 0
T3 14959 8887 0 0
T4 16586 3620 0 0
T5 20315 14813 0 0
T6 14554 11772 0 0
T7 14122 11378 0 0
T8 137746 79148 0 0
T9 126236 36909 0 0
T10 11913 6774 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6861518 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6861518 0 0
T1 1481 833 0 0
T2 4523 816 0 0
T3 3589 2150 0 0
T4 3980 1154 0 0
T5 4874 3586 0 0
T6 3492 2840 0 0
T7 3388 2745 0 0
T8 33061 19302 0 0
T9 30294 9302 0 0
T10 2857 1656 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6598487 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6598487 0 0
T1 1481 817 0 0
T2 4523 600 0 0
T3 3589 2176 0 0
T4 3980 866 0 0
T5 4874 3467 0 0
T6 3492 2538 0 0
T7 3388 2442 0 0
T8 33061 19072 0 0
T9 30294 9090 0 0
T10 2857 1630 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 52913567 26494132 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 52913567 26494132 0 0
T1 5932 3275 0 0
T2 18102 2413 0 0
T3 14359 8790 0 0
T4 15923 3474 0 0
T5 19506 13952 0 0
T6 13971 10446 0 0
T7 13556 9700 0 0
T8 132243 76562 0 0
T9 121155 37006 0 0
T10 11433 6554 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457537 13256947 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457537 13256947 0 0
T1 2966 1637 0 0
T2 9050 1205 0 0
T3 7178 4389 0 0
T4 7961 1737 0 0
T5 9753 7165 0 0
T6 6985 4940 0 0
T7 6778 4990 0 0
T8 66127 38260 0 0
T9 60583 18473 0 0
T10 5718 3276 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 26457722 13249160 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457722 13249160 0 0
T1 2966 1637 0 0
T2 9050 1205 0 0
T3 7179 4389 0 0
T4 7961 1737 0 0
T5 9748 7161 0 0
T6 6985 4695 0 0
T7 6778 4906 0 0
T8 66121 38257 0 0
T9 60596 18482 0 0
T10 5715 3221 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1669982 819575 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1669982 819575 0 0
T1 184 101 0 0
T2 564 73 0 0
T3 448 261 0 0
T4 496 106 0 0
T5 608 441 0 0
T6 435 303 0 0
T7 423 308 0 0
T8 4202 2407 0 0
T9 3801 1046 0 0
T10 356 195 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6602092 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6602092 0 0
T1 1481 817 0 0
T2 4523 600 0 0
T3 3589 2177 0 0
T4 3980 866 0 0
T5 4874 3574 0 0
T6 3492 2543 0 0
T7 3388 2470 0 0
T8 33061 19072 0 0
T9 30294 9100 0 0
T10 2857 1630 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6602731 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6602731 0 0
T1 1481 817 0 0
T2 4523 600 0 0
T3 3589 2177 0 0
T4 3980 866 0 0
T5 4874 3506 0 0
T6 3492 2518 0 0
T7 3388 2393 0 0
T8 33061 19072 0 0
T9 30294 9100 0 0
T10 2857 1610 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13228444 6610593 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13228444 6610593 0 0
T1 1481 817 0 0
T2 4523 600 0 0
T3 3589 2177 0 0
T4 3980 866 0 0
T5 4874 3574 0 0
T6 3492 2412 0 0
T7 3388 2503 0 0
T8 33061 19072 0 0
T9 30294 9090 0 0
T10 2857 1630 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1669982 995399 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1669982 995399 0 0
T1 184 105 0 0
T2 564 104 0 0
T3 448 369 0 0
T4 496 146 0 0
T5 608 484 0 0
T6 435 356 0 0
T7 423 344 0 0
T8 4202 2798 0 0
T9 3801 1555 0 0
T10 356 236 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 unreachable assign mubi = MuBi4Width'(mubi_i); 35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1669982 976216 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1669982 976216 0 0
T1 184 103 0 0
T2 564 77 0 0
T3 448 367 0 0
T4 496 110 0 0
T5 608 480 0 0
T6 435 354 0 0
T7 423 342 0 0
T8 4202 2758 0 0
T9 3801 1499 0 0
T10 356 232 0 0