Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12574523	8384	0	0
alert_regwen_rd_A	12574523	4819	0	0
cpu_regwen_rd_A	12574523	5060	0	0
sw_rst_ctrl_n_0_rd_A	12574523	9502	0	0
sw_rst_ctrl_n_1_rd_A	12574523	9533	0	0
sw_rst_ctrl_n_2_rd_A	12574523	9673	0	0
sw_rst_ctrl_n_3_rd_A	12574523	9612	0	0
sw_rst_ctrl_n_4_rd_A	12574523	9462	0	0
sw_rst_ctrl_n_5_rd_A	12574523	9677	0	0
sw_rst_ctrl_n_6_rd_A	12574523	9427	0	0
sw_rst_ctrl_n_7_rd_A	12574523	9535	0	0
sw_rst_regwen_0_rd_A	12574523	5209	0	0
sw_rst_regwen_1_rd_A	12574523	5220	0	0
sw_rst_regwen_2_rd_A	12574523	5334	0	0
sw_rst_regwen_3_rd_A	12574523	5434	0	0
sw_rst_regwen_4_rd_A	12574523	5059	0	0
sw_rst_regwen_5_rd_A	12574523	5272	0	0
sw_rst_regwen_6_rd_A	12574523	5227	0	0
sw_rst_regwen_7_rd_A	12574523	5114	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	8384	0	0
T55	3044	64	0	0
T63	9505	1	0	0
T64	4015	64	0	0
T65	2970	162	0	0
T69	19716	1	0	0
T71	4291	332	0	0
T72	4476	359	0	0
T74	7342	287	0	0
T75	21625	4	0	0
T81	18009	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	4819	0	0
T27	27065	0	0	0
T28	55446	0	0	0
T38	27081	0	0	0
T97	40449	78	0	0
T98	148986	0	0	0
T99	20689	0	0	0
T100	20857	0	0	0
T102	31336	0	0	0
T105	0	227	0	0
T107	0	198	0	0
T108	0	323	0	0
T121	0	434	0	0
T122	0	226	0	0
T123	0	26	0	0
T124	0	405	0	0
T125	0	52	0	0
T126	0	517	0	0
T127	2212	0	0	0
T128	3285	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5060	0	0
T27	27065	0	0	0
T28	55446	0	0	0
T38	27081	0	0	0
T97	40449	61	0	0
T98	148986	0	0	0
T99	20689	0	0	0
T100	20857	0	0	0
T102	31336	0	0	0
T105	0	219	0	0
T107	0	278	0	0
T108	0	297	0	0
T121	0	417	0	0
T122	0	256	0	0
T123	0	38	0	0
T124	0	425	0	0
T125	0	88	0	0
T126	0	440	0	0
T127	2212	0	0	0
T128	3285	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9502	0	0
T11	5893	5	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	9	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	146	0	0
T49	59681	0	0	0
T52	0	19	0	0
T87	0	117	0	0
T91	0	16	0	0
T92	0	17	0	0
T93	0	108	0	0
T97	0	32	0	0
T128	0	43	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9533	0	0
T11	5893	15	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	13	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	155	0	0
T49	59681	0	0	0
T52	0	13	0	0
T87	0	118	0	0
T91	0	20	0	0
T92	0	8	0	0
T93	0	123	0	0
T97	0	47	0	0
T128	0	29	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9673	0	0
T11	5893	19	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	20	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	132	0	0
T49	59681	0	0	0
T52	0	11	0	0
T87	0	139	0	0
T91	0	10	0	0
T92	0	17	0	0
T93	0	94	0	0
T97	0	44	0	0
T128	0	31	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9612	0	0
T11	5893	6	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	17	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	85	0	0
T49	59681	0	0	0
T52	0	14	0	0
T87	0	129	0	0
T91	0	13	0	0
T92	0	19	0	0
T93	0	104	0	0
T97	0	62	0	0
T128	0	37	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9462	0	0
T11	5893	8	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	7	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	86	0	0
T49	59681	0	0	0
T52	0	8	0	0
T87	0	125	0	0
T91	0	5	0	0
T92	0	18	0	0
T93	0	118	0	0
T97	0	45	0	0
T128	0	22	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9677	0	0
T11	5893	6	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	25	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	115	0	0
T49	59681	0	0	0
T52	0	14	0	0
T87	0	142	0	0
T91	0	23	0	0
T92	0	10	0	0
T93	0	123	0	0
T97	0	49	0	0
T128	0	10	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9427	0	0
T11	5893	14	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	6	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	98	0	0
T49	59681	0	0	0
T52	0	24	0	0
T87	0	119	0	0
T91	0	12	0	0
T92	0	3	0	0
T93	0	126	0	0
T97	0	39	0	0
T128	0	11	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	9535	0	0
T11	5893	15	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	12	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	130	0	0
T49	59681	0	0	0
T52	0	24	0	0
T87	0	111	0	0
T91	0	22	0	0
T92	0	12	0	0
T93	0	106	0	0
T97	0	54	0	0
T128	0	6	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5209	0	0
T11	5893	9	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	1	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	32	0	0
T49	59681	0	0	0
T52	0	14	0	0
T87	0	20	0	0
T91	0	10	0	0
T92	0	4	0	0
T93	0	34	0	0
T97	0	44	0	0
T129	0	30	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5220	0	0
T11	5893	18	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	8	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	25	0	0
T49	59681	0	0	0
T52	0	14	0	0
T87	0	4	0	0
T91	0	6	0	0
T92	0	8	0	0
T93	0	25	0	0
T97	0	55	0	0
T129	0	31	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5334	0	0
T11	5893	12	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	6	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	17	0	0
T49	59681	0	0	0
T52	0	3	0	0
T87	0	18	0	0
T91	0	8	0	0
T92	0	4	0	0
T93	0	27	0	0
T97	0	65	0	0
T129	0	29	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5434	0	0
T11	5893	6	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	2	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	20	0	0
T49	59681	0	0	0
T52	0	10	0	0
T87	0	29	0	0
T91	0	15	0	0
T92	0	14	0	0
T93	0	35	0	0
T97	0	56	0	0
T129	0	43	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5059	0	0
T11	5893	2	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	2	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	14	0	0
T49	59681	0	0	0
T52	0	8	0	0
T87	0	31	0	0
T91	0	4	0	0
T93	0	34	0	0
T97	0	36	0	0
T105	0	229	0	0
T129	0	18	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5272	0	0
T11	5893	2	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	8	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	11	0	0
T49	59681	0	0	0
T52	0	3	0	0
T87	0	24	0	0
T91	0	7	0	0
T92	0	13	0	0
T93	0	32	0	0
T97	0	50	0	0
T129	0	51	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5227	0	0
T11	5893	5	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	9	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	15	0	0
T49	59681	0	0	0
T52	0	5	0	0
T87	0	10	0	0
T91	0	4	0	0
T92	0	10	0	0
T93	0	46	0	0
T97	0	54	0	0
T129	0	47	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12574523	5114	0	0
T11	5893	7	0	0
T12	2224	0	0	0
T13	4352	0	0	0
T14	6516	0	0	0
T15	1807	0	0	0
T23	5816	10	0	0
T24	1700	0	0	0
T25	2042	0	0	0
T35	191776	0	0	0
T47	0	7	0	0
T49	59681	0	0	0
T52	0	2	0	0
T87	0	21	0	0
T91	0	2	0	0
T92	0	8	0	0
T93	0	19	0	0
T97	0	68	0	0
T129	0	23	0	0