Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7505

1

T2

8

T11

24

T12

19

auto[1]

10229

1

T2

1

T4

4

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5601	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5992	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2715	1			T4	1		T6	1		T8	1
reset_info_cp[4]	3510	1			T4	1		T6	1		T8	1
reset_info_cp[8]	105	1			T11	2		T13	1		T137	1
reset_info_cp[16]	108	1			T14	1		T25	1		T57	1
reset_info_cp[32]	104	1			T2	1		T12	1		T53	1
reset_info_cp[64]	100	1			T11	1		T13	1		T25	2
reset_info_cp[128]	96	1			T14	1		T25	1		T80	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2894	1			T11	8		T12	19		T13	15
reset_info_cp[1]	auto[1]	2501	1			T4	1		T6	1		T8	1
reset_info_cp[2]	auto[0]	846	1			T11	4		T14	13		T71	3
reset_info_cp[2]	auto[1]	1869	1			T4	1		T6	1		T8	1
reset_info_cp[4]	auto[0]	1261	1			T11	4		T14	12		T71	8
reset_info_cp[4]	auto[1]	2249	1			T4	1		T6	1		T8	1
reset_info_cp[8]	auto[0]	43	1			T11	1		T137	1		T147	1
reset_info_cp[8]	auto[1]	62	1			T11	1		T13	1		T148	1
reset_info_cp[16]	auto[0]	46	1			T14	1		T57	1		T77	1
reset_info_cp[16]	auto[1]	62	1			T25	1		T38	1		T27	1
reset_info_cp[32]	auto[0]	43	1			T53	1		T80	1		T95	1
reset_info_cp[32]	auto[1]	61	1			T2	1		T12	1		T95	1
reset_info_cp[64]	auto[0]	37	1			T80	1		T149	1		T148	2
reset_info_cp[64]	auto[1]	63	1			T11	1		T13	1		T25	2
reset_info_cp[128]	auto[0]	27	1			T14	1		T80	1		T96	1
reset_info_cp[128]	auto[1]	69	1			T25	1		T150	1		T142	2