| | | | | | | |
tb.dut.AlertsKnownO_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.ParameterMatch_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.PwrKnownO_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.ResetsKnownO_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.RstEnKnownO_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.TlAReadyKnownO_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.TlDValidKnownO_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A
| 0 | 0 | 10305812 | 60 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1472054 | 895876 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8281 | 7799 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 6278 | 5796 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1472054 | 879218 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A
| 0 | 0 | 10305812 | 12064 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A
| 0 | 0 | 10305812 | 111189 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A
| 0 | 0 | 10305812 | 6044025 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A
| 0 | 0 | 10305812 | 177439 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A
| 0 | 0 | 10305812 | 12064 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A
| 0 | 0 | 10305812 | 111189 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A
| 0 | 0 | 10305812 | 6044025 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A
| 0 | 0 | 10305812 | 177439 | 0 | 0 |
|
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A
| 0 | 0 | 48579864 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A
| 0 | 0 | 48579864 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A
| 0 | 0 | 46634603 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A
| 0 | 0 | 46634603 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A
| 0 | 0 | 23318350 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A
| 0 | 0 | 23318350 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A
| 0 | 0 | 11658812 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A
| 0 | 0 | 11658812 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A
| 0 | 0 | 23318412 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A
| 0 | 0 | 23318412 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A
| 0 | 0 | 1472054 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A
| 0 | 0 | 1472054 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A
| 0 | 0 | 1472054 | 6287 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A
| 0 | 0 | 1472054 | 188 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A
| 0 | 0 | 1472054 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A
| 0 | 0 | 11658812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A
| 0 | 0 | 11658812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A
| 0 | 0 | 10305812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A
| 0 | 0 | 11127646 | 8437 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A
| 0 | 0 | 11127646 | 4750 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A
| 0 | 0 | 11127646 | 4703 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A
| 0 | 0 | 11127646 | 9969 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A
| 0 | 0 | 11127646 | 9766 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A
| 0 | 0 | 11127646 | 9740 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A
| 0 | 0 | 11127646 | 9692 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A
| 0 | 0 | 11127646 | 9598 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A
| 0 | 0 | 11127646 | 9495 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A
| 0 | 0 | 11127646 | 9576 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A
| 0 | 0 | 11127646 | 9675 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A
| 0 | 0 | 11127646 | 5539 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A
| 0 | 0 | 11127646 | 5426 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A
| 0 | 0 | 11127646 | 5408 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A
| 0 | 0 | 11127646 | 5330 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A
| 0 | 0 | 11127646 | 5266 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A
| 0 | 0 | 11127646 | 5586 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A
| 0 | 0 | 11127646 | 5369 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A
| 0 | 0 | 11127646 | 5421 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A
| 0 | 0 | 11658812 | 13330 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A
| 0 | 0 | 11658812 | 21113 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A
| 0 | 0 | 11658812 | 13417 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A
| 0 | 0 | 11658812 | 21192 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A
| 0 | 0 | 11658812 | 13498 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A
| 0 | 0 | 11658812 | 21265 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A
| 0 | 0 | 23318350 | 12131 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A
| 0 | 0 | 23318350 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A
| 0 | 0 | 11658812 | 12159 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A
| 0 | 0 | 11658812 | 19996 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A
| 0 | 0 | 46634603 | 12132 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A
| 0 | 0 | 46634603 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A
| 0 | 0 | 48579864 | 12188 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A
| 0 | 0 | 48579864 | 19996 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A
| 0 | 0 | 23318412 | 12142 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A
| 0 | 0 | 23318412 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A
| 0 | 0 | 1472054 | 48 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A
| 0 | 0 | 1472054 | 7872 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A
| 0 | 0 | 11658812 | 13138 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A
| 0 | 0 | 11658812 | 20912 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A
| 0 | 0 | 46634603 | 13148 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A
| 0 | 0 | 46634603 | 20923 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A
| 0 | 0 | 23318350 | 13228 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A
| 0 | 0 | 23318350 | 21004 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A
| 0 | 0 | 48579864 | 12141 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A
| 0 | 0 | 48579864 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A
| 0 | 0 | 1472054 | 12900 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A
| 0 | 0 | 1472054 | 20214 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A
| 0 | 0 | 23318412 | 13273 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A
| 0 | 0 | 23318412 | 21048 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A
| 0 | 0 | 1472054 | 12090 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A
| 0 | 0 | 1472054 | 19936 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A
| 0 | 0 | 23318350 | 12095 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A
| 0 | 0 | 23318350 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A
| 0 | 0 | 11658812 | 12111 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A
| 0 | 0 | 11658812 | 19996 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A
| 0 | 0 | 46634603 | 12085 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A
| 0 | 0 | 46634603 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A
| 0 | 0 | 48579864 | 12133 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A
| 0 | 0 | 48579864 | 19996 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A
| 0 | 0 | 23318412 | 12090 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A
| 0 | 0 | 23318412 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A
| 0 | 0 | 1472054 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A
| 0 | 0 | 48579864 | 28 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A
| 0 | 0 | 23318350 | 25 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A
| 0 | 0 | 23318350 | 1964 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A
| 0 | 0 | 11658812 | 7885 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A
| 0 | 0 | 46634603 | 20 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A
| 0 | 0 | 23318412 | 16 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A
| 0 | 0 | 23318412 | 1964 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A
| 0 | 0 | 11658812 | 12085 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A
| 0 | 0 | 11658812 | 19949 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A
| 0 | 0 | 11658812 | 13026 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A
| 0 | 0 | 11658812 | 1141 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A
| 0 | 0 | 11658812 | 13026 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A
| 0 | 0 | 11658812 | 1141 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A
| 0 | 0 | 46634603 | 11838 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A
| 0 | 0 | 46634603 | 1083 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A
| 0 | 0 | 46634603 | 11838 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A
| 0 | 0 | 46634603 | 1083 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A
| 0 | 0 | 23318350 | 11923 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A
| 0 | 0 | 23318350 | 1098 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A
| 0 | 0 | 23318350 | 11923 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A
| 0 | 0 | 23318350 | 1098 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A
| 0 | 0 | 23318412 | 11964 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A
| 0 | 0 | 23318412 | 1131 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A
| 0 | 0 | 23318412 | 11964 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A
| 0 | 0 | 23318412 | 1131 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A
| 0 | 0 | 1472054 | 19800 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A
| 0 | 0 | 1472054 | 1167 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A
| 0 | 0 | 1472054 | 19800 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A
| 0 | 0 | 1472054 | 1167 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOff_A
| 0 | 0 | 11658812 | 13224 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A
| 0 | 0 | 11658812 | 1196 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOff_A
| 0 | 0 | 11658812 | 13224 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A
| 0 | 0 | 11658812 | 1196 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOff_A
| 0 | 0 | 11658812 | 13303 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A
| 0 | 0 | 11658812 | 1284 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOff_A
| 0 | 0 | 11658812 | 13303 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A
| 0 | 0 | 11658812 | 1284 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A
| 0 | 0 | 11658812 | 13375 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A
| 0 | 0 | 11658812 | 1360 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOff_A
| 0 | 0 | 11658812 | 13375 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A
| 0 | 0 | 11658812 | 1360 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 11127646 | 1046401 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 11127646 | 6572511 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 11127646 | 6572511 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 11127646 | 1823752 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 11127646 | 6572511 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 11127646 | 6572511 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 11128243 | 466966 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 11127646 | 5888 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 11128243 | 767540 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 11128243 | 930541 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 11127646 | 6506 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 11128243 | 1046550 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 11128243 | 1823941 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 11128243 | 1046550 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 11128243 | 1823941 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 11128243 | 1823941 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 11128243 | 1823941 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 11127646 | 3565 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 11127646 | 3060 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_alert_info.CntStoreSlot_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_alert_info.CntWidth_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_cpu_info.CntStoreSlot_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_cpu_info.CntWidth_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11658812 | 7025852 | 0 | 0 |
|
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11658812 | 7025852 | 0 | 0 |
|
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 5897737 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21109 | 20627 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 5891065 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21188 | 20706 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 5885013 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21260 | 20778 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 48579864 | 25277612 | 0 | 0 |
|
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 46634603 | 24266992 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318350 | 12124209 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 6037176 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 6037176 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 48579864 | 25277534 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318412 | 12124038 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 5880456 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 20911 | 20429 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 46634603 | 23664579 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 20918 | 20436 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318350 | 11827528 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21003 | 20521 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 48579864 | 25003334 | 0 | 0 |
|
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318412 | 11828350 | 0 | 0 |
|
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21044 | 20562 | 0 | 0 |
|
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19889 | 19407 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1472054 | 731608 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21067 | 20585 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 48579864 | 25933319 | 0 | 0 |
|
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19889 | 19407 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1472054 | 769009 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 46634603 | 24896388 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318350 | 12438641 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 6194566 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 6194566 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 48579864 | 25933557 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318412 | 12438962 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 48579864 | 29293334 | 0 | 0 |
|
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 46634603 | 28120560 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318350 | 14056819 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 7025852 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 23318412 | 14057201 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 7885 | 7403 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19996 | 19514 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 11658812 | 6128492 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 482 | 482 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 10305812 | 6007698 | 0 | 0 |
|
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 11127646 | 906898 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 11127646 | 906738 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 11127646 | 484590 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 597 | 597 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 11127646 | 422148 | 0 | 0 |
|
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 19949 | 19467 | 0 | 0 |
|
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2525 | 2043 | 0 | 0 |
|