Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total tests in report: 597
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.27 82.27 95.71 95.71 85.50 85.50 80.10 80.10 95.33 95.33 88.96 88.96 48.03 48.03 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.53904986
90.05 7.77 96.96 1.25 92.37 6.87 92.17 12.07 97.67 2.33 91.66 2.69 69.46 21.43 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2315984861
92.10 2.06 97.44 0.48 95.00 2.64 92.42 0.25 97.83 0.17 92.33 0.67 77.59 8.13 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.31293563
93.96 1.86 97.80 0.36 96.25 1.25 92.42 0.00 97.83 0.00 94.48 2.15 84.98 7.39 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2712227706
95.74 1.78 98.39 0.60 96.88 0.62 95.52 3.10 98.83 1.00 98.12 3.63 86.70 1.72 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3311250906
96.96 1.23 98.81 0.42 97.09 0.21 98.91 3.39 99.17 0.33 98.65 0.54 89.16 2.46 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.1675724663
97.80 0.84 99.05 0.24 98.40 1.32 98.99 0.08 99.83 0.67 98.65 0.00 91.87 2.71 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4035472969
98.17 0.37 99.05 0.00 98.40 0.00 98.99 0.00 99.83 0.00 98.65 0.00 94.09 2.22 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.240220572
98.45 0.28 99.05 0.00 98.40 0.00 99.58 0.59 99.83 0.00 98.79 0.13 95.07 0.99 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.658645925
98.70 0.25 99.11 0.06 98.61 0.21 99.58 0.00 99.83 0.00 98.79 0.00 96.31 1.23 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.326139385
98.91 0.21 99.11 0.00 98.61 0.00 99.58 0.00 99.83 0.00 99.06 0.27 97.29 0.99 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.967331386
99.08 0.16 99.11 0.00 98.61 0.00 99.58 0.00 99.83 0.00 99.06 0.00 98.28 0.99 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1265840978
99.21 0.14 99.40 0.30 98.96 0.35 99.75 0.17 99.83 0.00 99.06 0.00 98.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1869322400
99.31 0.09 99.40 0.00 99.03 0.07 99.75 0.00 99.83 0.00 99.06 0.00 98.77 0.49 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3525305555
99.37 0.06 99.40 0.00 99.03 0.00 100.00 0.25 99.83 0.00 99.19 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.1979804462
99.41 0.03 99.40 0.00 99.24 0.21 100.00 0.00 99.83 0.00 99.19 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.1930291318
99.43 0.02 99.40 0.00 99.24 0.00 100.00 0.00 99.83 0.00 99.33 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.4002031885
99.45 0.02 99.40 0.00 99.24 0.00 100.00 0.00 99.83 0.00 99.46 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3331759025
99.46 0.01 99.40 0.00 99.31 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1278222670

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3269310223
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2229368707
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2155463178
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.943405418
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2843852491
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3160360560
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3750209618
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3911101198
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2671634522
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1697690889
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2258578111
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1414285977
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1191420179
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2584624841
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3034646075
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1448701452
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2173447402
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1951118797
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1318651037
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.3899868784
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.699467298
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1358436199
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1986125632
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.734856062
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2170560027
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.908428592
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1814373771
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.768678410
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3862885775
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2309410544
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2148973624
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1565784468
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3109270225
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4286303081
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3460881854
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.774562927
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.4203947641
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.456033166
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2141657338
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3173968015
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3085353813
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3578661974
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4268311537
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2746872114
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1915471652
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2926793701
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2589638858
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.508588333
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2479485505
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.4232093677
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2086338532
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.224158620
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2551069455
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3599052211
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3408561220
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4076848005
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2512125780
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1614168463
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2132626779
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3166176529
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.257174562
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2148103910
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1015504252
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1024304332
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1186767244
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1402292241
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3342405443
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.3062492140
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.54169318
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2362698584
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2549133606
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.451557039
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2609489048
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.110930396
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1495749111
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3822027384
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1023458863
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.401212710
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.355529496
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1558086907
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3323952378
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1028966657
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3566258536
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4048337643
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.4095833176
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1978651356
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3717281103
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2042081315
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.867819705
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.409928760
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3236871359
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1564944103
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2286639776
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2447162950
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2594850614
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3666810454
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.2265903832
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2603685330
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.2025419805
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1046927690
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.566013917
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2435528724
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.40344236
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/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2084443561
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1795302143
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2675340300
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1596828184
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1638261166
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.2467141428
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.1419118370
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2966202546
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.762721173
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1023860477
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.4255612078
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2870381964
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1968427292
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.1884670872
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.4118674308
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4230881633
/workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1559135778



Total test records in report: 597
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3331759025 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 106865853 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1135586328 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 168530798 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1869322400 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 86123553 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1265840978 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 151606501 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3631784798 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 85647038 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.326139385 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 195065332 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.186553645 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 301487716 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.53904986 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:17 PM UTC 24 115814645 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1906240050 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:18 PM UTC 24 301492389 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3050014105 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:18 PM UTC 24 378486075 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1437967119 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:21 PM UTC 24 1336087155 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.658645925 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:21 PM UTC 24 1269500900 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.1675724663 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:23 PM UTC 24 1958430726 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2315984861 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:26 PM UTC 24 2593097238 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.2315222987 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:27 PM UTC 24 65163481 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2969990535 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:27 PM UTC 24 112244642 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.196810115 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:27 PM UTC 24 305707996 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1763135855 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:27 PM UTC 24 176694146 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.3645423401 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:28 PM UTC 24 8459887845 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.3115019030 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:28 PM UTC 24 267082711 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2456622905 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:28 PM UTC 24 150618903 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3311250906 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:29 PM UTC 24 8425642492 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1738747371 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:32 PM UTC 24 1698883900 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.1742275399 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:32 PM UTC 24 1215167700 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1988655346 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:32 PM UTC 24 88496340 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1371920930 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:32 PM UTC 24 76776088 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3045352137 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:32 PM UTC 24 153403584 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3340284060 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:32 PM UTC 24 301531443 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1423920434 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:33 PM UTC 24 114069770 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4116829792 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:33 PM UTC 24 126274185 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.644516726 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:33 PM UTC 24 1951879993 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2234644612 Sep 01 08:29:19 PM UTC 24 Sep 01 08:29:36 PM UTC 24 1037161486 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2077184583 Sep 01 08:29:34 PM UTC 24 Sep 01 08:29:37 PM UTC 24 60534450 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2084443561 Sep 01 08:29:34 PM UTC 24 Sep 01 08:29:37 PM UTC 24 72317614 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2593612818 Sep 01 08:29:32 PM UTC 24 Sep 01 08:29:37 PM UTC 24 301406461 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1596828184 Sep 01 08:29:34 PM UTC 24 Sep 01 08:29:38 PM UTC 24 114148459 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.9929544 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 94373185 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.1419118370 Sep 01 08:29:34 PM UTC 24 Sep 01 08:29:38 PM UTC 24 152699191 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3963845315 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:38 PM UTC 24 181494999 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.3855878309 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 70913142 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1927164051 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:38 PM UTC 24 156206297 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2090925531 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:38 PM UTC 24 197901899 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2712922796 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 96815027 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1219687736 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 64397487 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1205644197 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 196692447 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2105616261 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 223115488 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.154161878 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 301993421 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.2088870683 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 168320268 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.2467141428 Sep 01 08:29:34 PM UTC 24 Sep 01 08:29:38 PM UTC 24 146189722 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.612294989 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:38 PM UTC 24 114693692 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.2558668465 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:39 PM UTC 24 74272454 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2675340300 Sep 01 08:29:36 PM UTC 24 Sep 01 08:29:39 PM UTC 24 175155467 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3933265464 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:39 PM UTC 24 129909517 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.240220572 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:39 PM UTC 24 171490293 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.3675361633 Sep 01 08:29:30 PM UTC 24 Sep 01 08:29:39 PM UTC 24 112776078 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2712227706 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:39 PM UTC 24 455409568 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1344287496 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:39 PM UTC 24 129786941 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3917614304 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:39 PM UTC 24 144781340 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.2453917570 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:39 PM UTC 24 88330559 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.3751869182 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:39 PM UTC 24 2455836492 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2829727195 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:39 PM UTC 24 301944221 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2377792923 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:39 PM UTC 24 124202337 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.919479581 Sep 01 08:29:30 PM UTC 24 Sep 01 08:29:40 PM UTC 24 114657153 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1935272959 Sep 01 08:29:28 PM UTC 24 Sep 01 08:29:40 PM UTC 24 80742942 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.1979364502 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:40 PM UTC 24 161279278 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2086776538 Sep 01 08:29:28 PM UTC 24 Sep 01 08:29:40 PM UTC 24 302327481 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.1132741784 Sep 01 08:29:28 PM UTC 24 Sep 01 08:29:40 PM UTC 24 154650814 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.2509688415 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:40 PM UTC 24 464329103 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.2659561588 Sep 01 08:29:30 PM UTC 24 Sep 01 08:29:40 PM UTC 24 378155724 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2485353730 Sep 01 08:29:28 PM UTC 24 Sep 01 08:29:40 PM UTC 24 190074072 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3858314459 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 96692345 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.4255612078 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 179733048 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1330969274 Sep 01 08:29:22 PM UTC 24 Sep 01 08:29:41 PM UTC 24 113118146 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1559135778 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 105413927 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1968427292 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 145492997 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.427175084 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 301735882 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.1884670872 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 124991096 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.2418651523 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:41 PM UTC 24 809005207 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1023860477 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:41 PM UTC 24 301651715 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.627454327 Sep 01 08:29:22 PM UTC 24 Sep 01 08:29:42 PM UTC 24 159951265 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1023315394 Sep 01 08:29:12 PM UTC 24 Sep 01 08:29:42 PM UTC 24 1474544212 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4230881633 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:42 PM UTC 24 137204822 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3202039426 Sep 01 08:29:30 PM UTC 24 Sep 01 08:29:43 PM UTC 24 867753964 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1795302143 Sep 01 08:29:34 PM UTC 24 Sep 01 08:29:43 PM UTC 24 1773832604 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.918443615 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:43 PM UTC 24 112704563 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2966202546 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:43 PM UTC 24 68481661 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.112030508 Sep 01 08:29:48 PM UTC 24 Sep 01 08:29:57 PM UTC 24 122987446 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2870381964 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:43 PM UTC 24 699792660 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.144461789 Sep 01 08:29:48 PM UTC 24 Sep 01 08:29:58 PM UTC 24 314660212 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.955160667 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:43 PM UTC 24 136782669 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1537918596 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:44 PM UTC 24 95112332 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1822342921 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:55 PM UTC 24 6667787860 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.781275171 Sep 01 08:29:59 PM UTC 24 Sep 01 08:30:03 PM UTC 24 140360687 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3292046659 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 135566585 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.1345971653 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:44 PM UTC 24 191359249 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2082601719 Sep 01 08:29:32 PM UTC 24 Sep 01 08:29:44 PM UTC 24 2265847726 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.1943780473 Sep 01 08:29:50 PM UTC 24 Sep 01 08:29:57 PM UTC 24 1459368497 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.920574086 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:44 PM UTC 24 301692234 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.621724428 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 90699190 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2422574960 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 87232397 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.1414177390 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 125748465 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.258602078 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 171245006 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2295538543 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 100690636 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.536017768 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 83902748 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.3819110806 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:44 PM UTC 24 1942293629 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.2557035704 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:44 PM UTC 24 233193793 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2860443270 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:45 PM UTC 24 301698759 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3774698194 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:45 PM UTC 24 113441517 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.1979804462 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:45 PM UTC 24 1948472954 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2963098707 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:45 PM UTC 24 199652739 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.4182712189 Sep 01 08:29:20 PM UTC 24 Sep 01 08:29:45 PM UTC 24 2056052747 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.1993921162 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:45 PM UTC 24 539752346 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.3662517628 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:45 PM UTC 24 136526084 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.985304 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:45 PM UTC 24 317914182 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.3421846764 Sep 01 08:29:24 PM UTC 24 Sep 01 08:29:45 PM UTC 24 1279541015 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.786954592 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:46 PM UTC 24 2443381404 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.2854964444 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:46 PM UTC 24 1280245046 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.4224256553 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:47 PM UTC 24 861499117 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3506951932 Sep 01 08:29:48 PM UTC 24 Sep 01 08:29:57 PM UTC 24 302193566 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3917984108 Sep 01 08:29:44 PM UTC 24 Sep 01 08:29:47 PM UTC 24 67162925 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1638261166 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:47 PM UTC 24 1841506305 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.762721173 Sep 01 08:29:39 PM UTC 24 Sep 01 08:29:47 PM UTC 24 1964885123 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2801587416 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:47 PM UTC 24 126775472 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.1233525074 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:47 PM UTC 24 815205637 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1956409564 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:47 PM UTC 24 178944844 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.3102440049 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:03 PM UTC 24 203945952 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1147551184 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 302576175 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.2163173685 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 121827856 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.4146591907 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 130899821 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2815477983 Sep 01 08:29:44 PM UTC 24 Sep 01 08:29:48 PM UTC 24 302616874 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3883509005 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:48 PM UTC 24 1224325776 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2970759903 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 302371590 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.997235974 Sep 01 08:29:44 PM UTC 24 Sep 01 08:29:48 PM UTC 24 192362521 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.832824350 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 195118551 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.3410141222 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 84496116 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.3591382658 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 133914985 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.518074253 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 87029191 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2965448585 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 101994796 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.318196677 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 217332511 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3710531598 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:48 PM UTC 24 185694139 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.2794309810 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:49 PM UTC 24 1274037745 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.94702433 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:50 PM UTC 24 8986184871 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.1933955066 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:50 PM UTC 24 3398183595 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.112630352 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:51 PM UTC 24 2465836963 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.3595531540 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:51 PM UTC 24 2432137294 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.3891817312 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:52 PM UTC 24 1116290278 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.3413289392 Sep 01 08:29:17 PM UTC 24 Sep 01 08:29:52 PM UTC 24 8289889632 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.4118674308 Sep 01 08:29:41 PM UTC 24 Sep 01 08:29:52 PM UTC 24 2994096877 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.866392822 Sep 01 08:29:49 PM UTC 24 Sep 01 08:29:52 PM UTC 24 57993059 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1103371418 Sep 01 08:29:47 PM UTC 24 Sep 01 08:29:52 PM UTC 24 90159486 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3303320002 Sep 01 08:29:47 PM UTC 24 Sep 01 08:29:52 PM UTC 24 76325544 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.967331386 Sep 01 08:29:13 PM UTC 24 Sep 01 08:29:53 PM UTC 24 4345991304 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.701321719 Sep 01 08:29:50 PM UTC 24 Sep 01 08:29:53 PM UTC 24 102575507 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1619087304 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:53 PM UTC 24 1613509985 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1730397523 Sep 01 08:29:50 PM UTC 24 Sep 01 08:29:53 PM UTC 24 214577445 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.758064166 Sep 01 08:29:47 PM UTC 24 Sep 01 08:29:53 PM UTC 24 120327534 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.1484342948 Sep 01 08:29:49 PM UTC 24 Sep 01 08:29:53 PM UTC 24 194487671 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1840318194 Sep 01 08:29:28 PM UTC 24 Sep 01 08:29:53 PM UTC 24 3939022714 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3719683979 Sep 01 08:29:51 PM UTC 24 Sep 01 08:29:53 PM UTC 24 182279332 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.144504273 Sep 01 08:29:42 PM UTC 24 Sep 01 08:29:53 PM UTC 24 2452718027 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3169008137 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:54 PM UTC 24 1972499777 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.3680412325 Sep 01 08:29:51 PM UTC 24 Sep 01 08:29:54 PM UTC 24 392285713 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.3091930577 Sep 01 08:29:45 PM UTC 24 Sep 01 08:29:54 PM UTC 24 2257834533 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.205348488 Sep 01 08:29:44 PM UTC 24 Sep 01 08:29:54 PM UTC 24 2650430561 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.2304866677 Sep 01 08:29:47 PM UTC 24 Sep 01 08:29:59 PM UTC 24 817212646 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.909854615 Sep 01 08:29:59 PM UTC 24 Sep 01 08:30:02 PM UTC 24 181410533 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.1493117357 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:03 PM UTC 24 64496299 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.576316852 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:03 PM UTC 24 68204933 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2942240739 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:03 PM UTC 24 302333324 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.916043759 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:03 PM UTC 24 185447912 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4093173013 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:03 PM UTC 24 111529138 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.431449700 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:03 PM UTC 24 104025635 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.846075488 Sep 01 08:29:12 PM UTC 24 Sep 01 08:30:03 PM UTC 24 6711169454 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.3755295188 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:03 PM UTC 24 188957341 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.108083204 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:03 PM UTC 24 2453346248 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.2974434251 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:03 PM UTC 24 223163151 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4193571865 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:04 PM UTC 24 301745596 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.669202897 Sep 01 08:29:34 PM UTC 24 Sep 01 08:30:04 PM UTC 24 6799286035 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3028286750 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:04 PM UTC 24 231446341 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3952768478 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:04 PM UTC 24 250609920 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.3075362522 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:04 PM UTC 24 328909948 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1245051199 Sep 01 08:29:45 PM UTC 24 Sep 01 08:30:04 PM UTC 24 4228739405 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.3122544718 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:05 PM UTC 24 436785512 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.825068782 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:06 PM UTC 24 941077777 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.2747240359 Sep 01 08:29:13 PM UTC 24 Sep 01 08:30:07 PM UTC 24 16520702297 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.826214527 Sep 01 08:30:04 PM UTC 24 Sep 01 08:30:13 PM UTC 24 1582923568 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.2453895398 Sep 01 08:30:04 PM UTC 24 Sep 01 08:30:07 PM UTC 24 73532584 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.1356009672 Sep 01 08:29:55 PM UTC 24 Sep 01 08:30:07 PM UTC 24 155158100 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.2621455961 Sep 01 08:29:54 PM UTC 24 Sep 01 08:30:07 PM UTC 24 81324313 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3394287812 Sep 01 08:29:55 PM UTC 24 Sep 01 08:30:07 PM UTC 24 84534102 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.3121740380 Sep 01 08:29:52 PM UTC 24 Sep 01 08:30:07 PM UTC 24 86532370 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.2098985215 Sep 01 08:29:52 PM UTC 24 Sep 01 08:30:07 PM UTC 24 74658235 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3133395789 Sep 01 08:29:54 PM UTC 24 Sep 01 08:30:07 PM UTC 24 301327720 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3385761686 Sep 01 08:29:54 PM UTC 24 Sep 01 08:30:07 PM UTC 24 124697610 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3317410967 Sep 01 08:29:55 PM UTC 24 Sep 01 08:30:07 PM UTC 24 103775354 ps
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T251 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1852602627 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:07 PM UTC 24 174205284 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.209090350 Sep 01 08:29:52 PM UTC 24 Sep 01 08:30:08 PM UTC 24 120321161 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.187028935 Sep 01 08:29:54 PM UTC 24 Sep 01 08:30:08 PM UTC 24 101113459 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.756263140 Sep 01 08:30:04 PM UTC 24 Sep 01 08:30:08 PM UTC 24 179369673 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3799447392 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:13 PM UTC 24 351868766 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.3576632503 Sep 01 08:29:52 PM UTC 24 Sep 01 08:30:13 PM UTC 24 1946591982 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.544871176 Sep 01 08:29:52 PM UTC 24 Sep 01 08:30:08 PM UTC 24 117994101 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4157236884 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:08 PM UTC 24 302332802 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1128956866 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:08 PM UTC 24 67612041 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2106740372 Sep 01 08:30:04 PM UTC 24 Sep 01 08:30:08 PM UTC 24 124817437 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.819652285 Sep 01 08:29:55 PM UTC 24 Sep 01 08:30:08 PM UTC 24 138329319 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2328525475 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:08 PM UTC 24 171201440 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.1508216723 Sep 01 08:29:52 PM UTC 24 Sep 01 08:30:08 PM UTC 24 320411496 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3390820893 Sep 01 08:30:06 PM UTC 24 Sep 01 08:30:08 PM UTC 24 105701882 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3242535279 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:08 PM UTC 24 206404758 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.994417803 Sep 01 08:30:03 PM UTC 24 Sep 01 08:30:08 PM UTC 24 71916030 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4229091957 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:08 PM UTC 24 301322582 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.1083722250 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:08 PM UTC 24 217855983 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.180419504 Sep 01 08:29:55 PM UTC 24 Sep 01 08:30:08 PM UTC 24 302533172 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.692483222 Sep 01 08:30:06 PM UTC 24 Sep 01 08:30:09 PM UTC 24 301368519 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.316575832 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:09 PM UTC 24 113277282 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.2722416644 Sep 01 08:29:59 PM UTC 24 Sep 01 08:30:09 PM UTC 24 83123901 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3497479155 Sep 01 08:29:57 PM UTC 24 Sep 01 08:30:09 PM UTC 24 70946964 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2726497348 Sep 01 08:30:03 PM UTC 24 Sep 01 08:30:09 PM UTC 24 301823114 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.2580925431 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:09 PM UTC 24 136952949 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.1883623212 Sep 01 08:29:57 PM UTC 24 Sep 01 08:30:09 PM UTC 24 142616701 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.882357511 Sep 01 08:30:07 PM UTC 24 Sep 01 08:30:09 PM UTC 24 58321978 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.1288817018 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:09 PM UTC 24 1963000858 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1426436869 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:09 PM UTC 24 1982208685 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.1010253013 Sep 01 08:29:57 PM UTC 24 Sep 01 08:30:10 PM UTC 24 121497456 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.2400025957 Sep 01 08:30:04 PM UTC 24 Sep 01 08:30:10 PM UTC 24 502040015 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.2473049559 Sep 01 08:30:07 PM UTC 24 Sep 01 08:30:10 PM UTC 24 188318881 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.3608495524 Sep 01 08:29:55 PM UTC 24 Sep 01 08:30:10 PM UTC 24 640651059 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.473607969 Sep 01 08:30:08 PM UTC 24 Sep 01 08:30:10 PM UTC 24 182375507 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.749703079 Sep 01 08:30:08 PM UTC 24 Sep 01 08:30:11 PM UTC 24 100240555 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.1901602264 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:11 PM UTC 24 67581499 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3065970910 Sep 01 08:30:08 PM UTC 24 Sep 01 08:30:11 PM UTC 24 140317359 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.922601720 Sep 01 08:29:48 PM UTC 24 Sep 01 08:30:11 PM UTC 24 2034515278 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.976046150 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:11 PM UTC 24 87942867 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3719958403 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:11 PM UTC 24 119581188 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3005580656 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:11 PM UTC 24 97027924 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1492606194 Sep 01 08:30:08 PM UTC 24 Sep 01 08:30:11 PM UTC 24 302317565 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.2938361771 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:11 PM UTC 24 112568119 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.292330393 Sep 01 08:29:59 PM UTC 24 Sep 01 08:30:11 PM UTC 24 694166269 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.1766834107 Sep 01 08:29:51 PM UTC 24 Sep 01 08:30:11 PM UTC 24 2430626689 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3945151116 Sep 01 08:30:09 PM UTC 24 Sep 01 08:30:11 PM UTC 24 225749477 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.434640988 Sep 01 08:30:08 PM UTC 24 Sep 01 08:30:12 PM UTC 24 295571866 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.3034997462 Sep 01 08:30:10 PM UTC 24 Sep 01 08:30:12 PM UTC 24 136191407 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.2627527282 Sep 01 08:30:06 PM UTC 24 Sep 01 08:30:13 PM UTC 24 1275996136 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1965482002 Sep 01 08:30:10 PM UTC 24 Sep 01 08:30:13 PM UTC 24 301867104 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3122610683 Sep 01 08:30:05 PM UTC 24 Sep 01 08:30:13 PM UTC 24 1271997130 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3064591817 Sep 01 08:30:10 PM UTC 24 Sep 01 08:30:13 PM UTC 24 77568494 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2512462557 Sep 01 08:30:10 PM UTC 24 Sep 01 08:30:13 PM UTC 24 66082709 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3762834270 Sep 01 08:30:10 PM UTC 24 Sep 01 08:30:13 PM UTC 24 134200250 ps
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