| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 82.27 | 82.27 | 95.71 | 95.71 | 85.50 | 85.50 | 80.10 | 80.10 | 95.33 | 95.33 | 88.96 | 88.96 | 48.03 | 48.03 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.53904986 | ||
| 90.05 | 7.77 | 96.96 | 1.25 | 92.37 | 6.87 | 92.17 | 12.07 | 97.67 | 2.33 | 91.66 | 2.69 | 69.46 | 21.43 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2315984861 | ||
| 92.10 | 2.06 | 97.44 | 0.48 | 95.00 | 2.64 | 92.42 | 0.25 | 97.83 | 0.17 | 92.33 | 0.67 | 77.59 | 8.13 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.31293563 | ||
| 93.96 | 1.86 | 97.80 | 0.36 | 96.25 | 1.25 | 92.42 | 0.00 | 97.83 | 0.00 | 94.48 | 2.15 | 84.98 | 7.39 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2712227706 | ||
| 95.74 | 1.78 | 98.39 | 0.60 | 96.88 | 0.62 | 95.52 | 3.10 | 98.83 | 1.00 | 98.12 | 3.63 | 86.70 | 1.72 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3311250906 | ||
| 96.96 | 1.23 | 98.81 | 0.42 | 97.09 | 0.21 | 98.91 | 3.39 | 99.17 | 0.33 | 98.65 | 0.54 | 89.16 | 2.46 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.1675724663 | ||
| 97.80 | 0.84 | 99.05 | 0.24 | 98.40 | 1.32 | 98.99 | 0.08 | 99.83 | 0.67 | 98.65 | 0.00 | 91.87 | 2.71 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4035472969 | ||
| 98.17 | 0.37 | 99.05 | 0.00 | 98.40 | 0.00 | 98.99 | 0.00 | 99.83 | 0.00 | 98.65 | 0.00 | 94.09 | 2.22 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.240220572 | ||
| 98.45 | 0.28 | 99.05 | 0.00 | 98.40 | 0.00 | 99.58 | 0.59 | 99.83 | 0.00 | 98.79 | 0.13 | 95.07 | 0.99 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.658645925 | ||
| 98.70 | 0.25 | 99.11 | 0.06 | 98.61 | 0.21 | 99.58 | 0.00 | 99.83 | 0.00 | 98.79 | 0.00 | 96.31 | 1.23 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.326139385 | ||
| 98.91 | 0.21 | 99.11 | 0.00 | 98.61 | 0.00 | 99.58 | 0.00 | 99.83 | 0.00 | 99.06 | 0.27 | 97.29 | 0.99 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.967331386 | ||
| 99.08 | 0.16 | 99.11 | 0.00 | 98.61 | 0.00 | 99.58 | 0.00 | 99.83 | 0.00 | 99.06 | 0.00 | 98.28 | 0.99 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1265840978 | ||
| 99.21 | 0.14 | 99.40 | 0.30 | 98.96 | 0.35 | 99.75 | 0.17 | 99.83 | 0.00 | 99.06 | 0.00 | 98.28 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1869322400 | ||
| 99.31 | 0.09 | 99.40 | 0.00 | 99.03 | 0.07 | 99.75 | 0.00 | 99.83 | 0.00 | 99.06 | 0.00 | 98.77 | 0.49 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3525305555 | ||
| 99.37 | 0.06 | 99.40 | 0.00 | 99.03 | 0.00 | 100.00 | 0.25 | 99.83 | 0.00 | 99.19 | 0.13 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.1979804462 | ||
| 99.41 | 0.03 | 99.40 | 0.00 | 99.24 | 0.21 | 100.00 | 0.00 | 99.83 | 0.00 | 99.19 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.1930291318 | ||
| 99.43 | 0.02 | 99.40 | 0.00 | 99.24 | 0.00 | 100.00 | 0.00 | 99.83 | 0.00 | 99.33 | 0.13 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.4002031885 | ||
| 99.45 | 0.02 | 99.40 | 0.00 | 99.24 | 0.00 | 100.00 | 0.00 | 99.83 | 0.00 | 99.46 | 0.13 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3331759025 | ||
| 99.46 | 0.01 | 99.40 | 0.00 | 99.31 | 0.07 | 100.00 | 0.00 | 99.83 | 0.00 | 99.46 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1278222670 | ||
| Name |
|---|
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2155463178 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.943405418 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2843852491 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3160360560 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3750209618 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3911101198 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2671634522 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1697690889 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2258578111 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1414285977 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1191420179 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2584624841 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3034646075 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1448701452 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2173447402 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1951118797 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1318651037 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.3899868784 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.699467298 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1358436199 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1986125632 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.734856062 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2170560027 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1814373771 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.768678410 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3862885775 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2309410544 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3460881854 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2589638858 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.508588333 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.4232093677 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3166176529 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2148103910 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1015504252 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1402292241 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3342405443 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.3062492140 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1344287496 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2234644612 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3045352137 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2377792923 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1822342921 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1423920434 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1988655346 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1935272959 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.3421846764 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2086776538 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.2453917570 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.4182712189 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1330969274 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4116829792 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1840318194 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.627454327 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.1979364502 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2077184583 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2082601719 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2593612818 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.1132741784 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3202039426 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.919479581 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2485353730 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.669202897 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.2659561588 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.3675361633 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3858314459 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.2854964444 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.427175084 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2084443561 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1795302143 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2675340300 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1596828184 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1638261166 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.2467141428 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.1419118370 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2966202546 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.762721173 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1023860477 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.4255612078 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2870381964 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1968427292 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.1884670872 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.4118674308 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4230881633 |
| /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1559135778 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3331759025 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 106865853 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1135586328 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 168530798 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1869322400 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 86123553 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1265840978 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 151606501 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3631784798 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 85647038 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.326139385 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 195065332 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.186553645 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 301487716 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.53904986 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:17 PM UTC 24 | 115814645 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1906240050 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:18 PM UTC 24 | 301492389 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3050014105 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:18 PM UTC 24 | 378486075 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1437967119 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:21 PM UTC 24 | 1336087155 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.658645925 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:21 PM UTC 24 | 1269500900 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.1675724663 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:23 PM UTC 24 | 1958430726 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2315984861 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:26 PM UTC 24 | 2593097238 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.2315222987 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:27 PM UTC 24 | 65163481 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2969990535 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:27 PM UTC 24 | 112244642 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.196810115 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:27 PM UTC 24 | 305707996 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1763135855 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:27 PM UTC 24 | 176694146 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.3645423401 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:28 PM UTC 24 | 8459887845 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.3115019030 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:28 PM UTC 24 | 267082711 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2456622905 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:28 PM UTC 24 | 150618903 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3311250906 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:29 PM UTC 24 | 8425642492 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1738747371 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:32 PM UTC 24 | 1698883900 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.1742275399 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:32 PM UTC 24 | 1215167700 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1988655346 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:32 PM UTC 24 | 88496340 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1371920930 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:32 PM UTC 24 | 76776088 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3045352137 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:32 PM UTC 24 | 153403584 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3340284060 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:32 PM UTC 24 | 301531443 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1423920434 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:33 PM UTC 24 | 114069770 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4116829792 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:33 PM UTC 24 | 126274185 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.644516726 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:33 PM UTC 24 | 1951879993 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2234644612 | Sep 01 08:29:19 PM UTC 24 | Sep 01 08:29:36 PM UTC 24 | 1037161486 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2077184583 | Sep 01 08:29:34 PM UTC 24 | Sep 01 08:29:37 PM UTC 24 | 60534450 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2084443561 | Sep 01 08:29:34 PM UTC 24 | Sep 01 08:29:37 PM UTC 24 | 72317614 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2593612818 | Sep 01 08:29:32 PM UTC 24 | Sep 01 08:29:37 PM UTC 24 | 301406461 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1596828184 | Sep 01 08:29:34 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 114148459 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.9929544 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 94373185 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.1419118370 | Sep 01 08:29:34 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 152699191 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3963845315 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 181494999 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.3855878309 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 70913142 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1927164051 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 156206297 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2090925531 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 197901899 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2712922796 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 96815027 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1219687736 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 64397487 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1205644197 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 196692447 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2105616261 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 223115488 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.154161878 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 301993421 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.2088870683 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 168320268 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.2467141428 | Sep 01 08:29:34 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 146189722 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.612294989 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:38 PM UTC 24 | 114693692 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.2558668465 | Sep 01 08:29:17 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 74272454 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2675340300 | Sep 01 08:29:36 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 175155467 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3933265464 | Sep 01 08:29:13 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 129909517 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.240220572 | Sep 01 08:29:17 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 171490293 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.3675361633 | Sep 01 08:29:30 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 112776078 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2712227706 | Sep 01 08:29:12 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 455409568 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1344287496 | Sep 01 08:29:17 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 129786941 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3917614304 | Sep 01 08:29:17 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 144781340 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.2453917570 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 88330559 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.3751869182 | Sep 01 08:29:20 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 2455836492 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2829727195 | Sep 01 08:29:17 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 301944221 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2377792923 | Sep 01 08:29:17 PM UTC 24 | Sep 01 08:29:39 PM UTC 24 | 124202337 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.919479581 | Sep 01 08:29:30 PM UTC 24 | Sep 01 08:29:40 PM UTC 24 | 114657153 ps | ||
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| T175 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1537918596 | Sep 01 08:29:41 PM UTC 24 | Sep 01 08:29:44 PM UTC 24 | 95112332 ps | ||
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| T179 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.920574086 | Sep 01 08:29:41 PM UTC 24 | Sep 01 08:29:44 PM UTC 24 | 301692234 ps | ||
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| T181 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2422574960 | Sep 01 08:29:42 PM UTC 24 | Sep 01 08:29:44 PM UTC 24 | 87232397 ps | ||
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| T143 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1956409564 | Sep 01 08:29:45 PM UTC 24 | Sep 01 08:29:47 PM UTC 24 | 178944844 ps | ||
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| T218 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3719683979 | Sep 01 08:29:51 PM UTC 24 | Sep 01 08:29:53 PM UTC 24 | 182279332 ps | ||
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| T225 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2942240739 | Sep 01 08:29:51 PM UTC 24 | Sep 01 08:30:03 PM UTC 24 | 302333324 ps | ||
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| T239 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.825068782 | Sep 01 08:29:48 PM UTC 24 | Sep 01 08:30:06 PM UTC 24 | 941077777 ps | ||
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| T243 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.2621455961 | Sep 01 08:29:54 PM UTC 24 | Sep 01 08:30:07 PM UTC 24 | 81324313 ps | ||
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| T247 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3133395789 | Sep 01 08:29:54 PM UTC 24 | Sep 01 08:30:07 PM UTC 24 | 301327720 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3385761686 | Sep 01 08:29:54 PM UTC 24 | Sep 01 08:30:07 PM UTC 24 | 124697610 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3317410967 | Sep 01 08:29:55 PM UTC 24 | Sep 01 08:30:07 PM UTC 24 | 103775354 ps | ||
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| T252 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.209090350 | Sep 01 08:29:52 PM UTC 24 | Sep 01 08:30:08 PM UTC 24 | 120321161 ps | ||
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| T257 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4157236884 | Sep 01 08:29:48 PM UTC 24 | Sep 01 08:30:08 PM UTC 24 | 302332802 ps | ||
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| T261 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2328525475 | Sep 01 08:30:05 PM UTC 24 | Sep 01 08:30:08 PM UTC 24 | 171201440 ps | ||
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| T264 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3242535279 | Sep 01 08:30:05 PM UTC 24 | Sep 01 08:30:08 PM UTC 24 | 206404758 ps | ||
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| T267 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.1083722250 | Sep 01 08:30:05 PM UTC 24 | Sep 01 08:30:08 PM UTC 24 | 217855983 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.180419504 | Sep 01 08:29:55 PM UTC 24 | Sep 01 08:30:08 PM UTC 24 | 302533172 ps | ||
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| T285 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3065970910 | Sep 01 08:30:08 PM UTC 24 | Sep 01 08:30:11 PM UTC 24 | 140317359 ps | ||
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| T296 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1965482002 | Sep 01 08:30:10 PM UTC 24 | Sep 01 08:30:13 PM UTC 24 | 301867104 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3122610683 | Sep 01 08:30:05 PM UTC 24 | Sep 01 08:30:13 PM UTC 24 | 1271997130 ps | ||
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| T298 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2512462557 | Sep 01 08:30:10 PM UTC 24 | Sep 01 08:30:13 PM UTC 24 | 66082709 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3762834270 | Sep 01 08:30:10 PM UTC 24 | Sep 01 08:30:13 PM UTC 24 | 134200250 ps |
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