| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T91 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2541642821 | Sep 01 08:31:24 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 115789674 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3034646075 | Sep 01 08:31:26 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 82287228 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.110930396 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 96105923 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2240492149 | Sep 01 08:31:23 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 234911625 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2170560027 | Sep 01 08:31:39 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 58450278 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3822027384 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 62036538 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3460881854 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 61996329 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.3899868784 | Sep 01 08:31:35 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 65737614 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3566258536 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 61737302 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.4002031885 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 63441909 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.699467298 | Sep 01 08:31:35 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 76778254 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2155463178 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 84781378 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3911101198 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 86900408 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1564944103 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 113497789 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1495749111 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 141204898 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3323952378 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 109248784 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.2265903832 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 69111759 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1448701452 | Sep 01 08:31:26 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 247206229 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1023458863 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:39 PM UTC 24 | 115616621 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3772687619 | Sep 01 08:31:22 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 522111823 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1951118797 | Sep 01 08:31:26 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 471626515 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2258578111 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 121277530 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2843852491 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 110939725 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.943405418 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 194993359 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4048337643 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 158497603 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2173447402 | Sep 01 08:31:26 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 273162624 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.2025419805 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 123486904 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1028966657 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 102817321 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.401212710 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 587367663 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1986125632 | Sep 01 08:31:34 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 813952537 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.566013917 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 75231929 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3173968015 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 54698435 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1046927690 | Sep 01 08:31:20 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 138531280 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3160360560 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 157332002 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1191420179 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 456405736 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2603685330 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:40 PM UTC 24 | 221497867 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.451557039 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 430361125 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1278222670 | Sep 01 08:31:18 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 1006168798 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2435528724 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 100366020 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2042081315 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 74992043 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1402292241 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 108196256 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.355529496 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 357197298 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2286639776 | Sep 01 08:31:18 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 72325106 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.182929484 | Sep 01 08:31:21 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 446615698 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.867819705 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 139864867 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1318651037 | Sep 01 08:31:37 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 144788249 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3717281103 | Sep 01 08:31:17 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 197662348 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2671634522 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 122111487 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2362698584 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 97732293 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3525305555 | Sep 01 08:31:19 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 796861191 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3236871359 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 487284464 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2584624841 | Sep 01 08:31:27 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 190955527 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.908428592 | Sep 01 08:31:39 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 129736214 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2447162950 | Sep 01 08:31:18 PM UTC 24 | Sep 01 08:31:41 PM UTC 24 | 243000483 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2549133606 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 516283502 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1414285977 | Sep 01 08:31:13 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 507531090 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.409928760 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 190065888 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.768678410 | Sep 01 08:31:38 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 492370373 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2594850614 | Sep 01 08:31:18 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 341115756 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2309410544 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 76897907 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.734856062 | Sep 01 08:31:39 PM UTC 24 | Sep 01 08:31:42 PM UTC 24 | 187322428 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1814373771 | Sep 01 08:31:37 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 452960472 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3862885775 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 200899248 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4286303081 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 132900681 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1358436199 | Sep 01 08:31:34 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 567195731 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.4203947641 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 173782677 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3085353813 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 135447550 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1565784468 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 179665095 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2141657338 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 141275191 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.4232093677 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 90741488 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2746872114 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 111077178 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2148973624 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 251083341 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1915471652 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:43 PM UTC 24 | 80331541 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3109270225 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 479875888 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.774562927 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 210273540 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2926793701 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 139329227 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1558086907 | Sep 01 08:31:16 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 493165282 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2609489048 | Sep 01 08:31:15 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 492117615 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3578661974 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 143611543 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.508588333 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 537623639 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2551069455 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:44 PM UTC 24 | 479828398 ps | ||
| T583 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.456033166 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:45 PM UTC 24 | 922030660 ps | ||
| T584 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.224158620 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:45 PM UTC 24 | 354744227 ps | ||
| T585 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4268311537 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:45 PM UTC 24 | 878070032 ps | ||
| T586 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2589638858 | Sep 01 08:31:41 PM UTC 24 | Sep 01 08:31:45 PM UTC 24 | 546984120 ps | ||
| T587 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3408561220 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 75446341 ps | ||
| T588 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2086338532 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 88403820 ps | ||
| T589 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3166176529 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 65397655 ps | ||
| T590 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2479485505 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 113956850 ps | ||
| T591 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4076848005 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 79616244 ps | ||
| T592 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3599052211 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 202652461 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2132626779 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 113748126 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.257174562 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:46 PM UTC 24 | 82063553 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1015504252 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:47 PM UTC 24 | 509319308 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1614168463 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:48 PM UTC 24 | 822792989 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2512125780 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:48 PM UTC 24 | 466237272 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2148103910 | Sep 01 08:31:44 PM UTC 24 | Sep 01 08:31:49 PM UTC 24 | 570578091 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.53904986 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 115814645 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53904986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.53904986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2315984861 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2593097238 ps |
| CPU time | 9.89 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:26 PM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315984861 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2315984861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.31293563 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 555448144 ps |
| CPU time | 3.19 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:20 PM UTC 24 |
| Peak memory | 217752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31293563 -assert nopostproc +UVM_TESTNAME=rstmgr_bas e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.31293563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2712227706 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 455409568 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712227706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2712227706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3311250906 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8425642492 ps |
| CPU time | 12.06 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:29 PM UTC 24 |
| Peak memory | 241556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311250906 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3311250906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.1675724663 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1958430726 ps |
| CPU time | 6.67 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:23 PM UTC 24 |
| Peak memory | 241732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675724663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1675724663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4035472969 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1202213944 ps |
| CPU time | 3.85 seconds |
| Started | Sep 01 08:31:12 PM UTC 24 |
| Finished | Sep 01 08:31:17 PM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035472969 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.4035472969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.240220572 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 171490293 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240220572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.240220572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.658645925 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1269500900 ps |
| CPU time | 5.08 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:21 PM UTC 24 |
| Peak memory | 241704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658645925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.658645925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.326139385 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 195065332 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326139385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.326139385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.967331386 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4345991304 ps |
| CPU time | 15.22 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967331386 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.967331386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1265840978 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 151606501 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265840978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1265840978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1869322400 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 86123553 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869322400 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1869322400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3525305555 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 796861191 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525305555 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.3525305555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.1979804462 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1948472954 ps |
| CPU time | 6.81 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 242320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979804462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1979804462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.1930291318 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 313107271 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 08:31:12 PM UTC 24 |
| Finished | Sep 01 08:31:15 PM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930291318 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1930291318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.4002031885 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 63441909 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002031885 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4002031885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3331759025 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 106865853 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331759025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3331759025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1278222670 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1006168798 ps |
| CPU time | 3 seconds |
| Started | Sep 01 08:31:18 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278222670 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.1278222670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3269310223 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 116240027 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:33 PM UTC 24 |
| Peak memory | 206060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269310223 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3269310223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2229368707 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 799448792 ps |
| CPU time | 4.32 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229368707 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2229368707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2155463178 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 84781378 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155463178 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2155463178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.943405418 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 194993359 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=943405418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_wi th_rand_reset.943405418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2843852491 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 110939725 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843852491 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.2843852491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3160360560 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 157332002 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160360560 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3160360560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3750209618 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2293335110 ps |
| CPU time | 9.52 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:24 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750209618 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3750209618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3911101198 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 86900408 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911101198 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3911101198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2671634522 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 122111487 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2671634522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.2671634522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1697690889 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 89323540 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:21 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697690889 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1697690889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2258578111 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 121277530 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258578111 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.2258578111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1414285977 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 507531090 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 217640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414285977 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1414285977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1191420179 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 456405736 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191420179 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.1191420179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2584624841 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 190955527 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 08:31:27 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2584624841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.2584624841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3034646075 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 82287228 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:31:26 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034646075 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3034646075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1448701452 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 247206229 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 08:31:26 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448701452 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1448701452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2173447402 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 273162624 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 08:31:26 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 219632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173447402 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2173447402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1951118797 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 471626515 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 08:31:26 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951118797 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1951118797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1318651037 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 144788249 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:31:37 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1318651037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.1318651037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.3899868784 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 65737614 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:31:35 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899868784 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3899868784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.699467298 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 76778254 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:31:35 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699467298 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.699467298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1358436199 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 567195731 ps |
| CPU time | 3.26 seconds |
| Started | Sep 01 08:31:34 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358436199 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1358436199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1986125632 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 813952537 ps |
| CPU time | 2.61 seconds |
| Started | Sep 01 08:31:34 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986125632 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.1986125632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.734856062 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 187322428 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 08:31:39 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=734856062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_w ith_rand_reset.734856062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2170560027 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 58450278 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:31:39 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170560027 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2170560027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.908428592 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 129736214 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:31:39 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908428592 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.908428592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1814373771 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 452960472 ps |
| CPU time | 3.08 seconds |
| Started | Sep 01 08:31:37 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814373771 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1814373771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.768678410 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 492370373 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 08:31:38 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768678410 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.768678410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3862885775 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 200899248 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3862885775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.3862885775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2309410544 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 76897907 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309410544 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2309410544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2148973624 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 251083341 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148973624 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.2148973624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1565784468 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 179665095 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 219680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565784468 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1565784468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3109270225 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 479875888 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 207648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109270225 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.3109270225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4286303081 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 132900681 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4286303081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.4286303081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3460881854 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 61996329 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460881854 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3460881854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.774562927 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 210273540 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774562927 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.774562927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.4203947641 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 173782677 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203947641 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4203947641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.456033166 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 922030660 ps |
| CPU time | 2.82 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:45 PM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456033166 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.456033166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2141657338 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 141275191 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2141657338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.2141657338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3173968015 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 54698435 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173968015 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3173968015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3085353813 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 135447550 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085353813 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3085353813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3578661974 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 143611543 ps |
| CPU time | 2 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 217628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578661974 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3578661974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4268311537 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 878070032 ps |
| CPU time | 3.28 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:45 PM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268311537 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.4268311537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2746872114 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 111077178 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2746872114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.2746872114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1915471652 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 80331541 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915471652 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1915471652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2926793701 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 139329227 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 207792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926793701 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.2926793701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2589638858 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 546984120 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:45 PM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589638858 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2589638858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.508588333 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 537623639 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 207612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508588333 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.508588333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2479485505 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 113956850 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2479485505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.2479485505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.4232093677 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 90741488 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232093677 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4232093677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2086338532 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 88403820 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086338532 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.2086338532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.224158620 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 354744227 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:45 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224158620 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.224158620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2551069455 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 479828398 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 08:31:41 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 207648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551069455 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.2551069455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3599052211 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 202652461 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3599052211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_ with_rand_reset.3599052211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3408561220 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 75446341 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408561220 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3408561220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4076848005 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 79616244 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076848005 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.4076848005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2512125780 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 466237272 ps |
| CPU time | 3.15 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:48 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512125780 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2512125780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1614168463 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 822792989 ps |
| CPU time | 2.76 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:48 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614168463 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.1614168463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2132626779 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 113748126 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2132626779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.2132626779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3166176529 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 65397655 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166176529 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3166176529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.257174562 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 82063553 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257174562 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.257174562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2148103910 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 570578091 ps |
| CPU time | 3.52 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:49 PM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148103910 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2148103910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1015504252 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 509319308 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015504252 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.1015504252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1024304332 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 198698507 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 207664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024304332 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1024304332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1186767244 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2300507251 ps |
| CPU time | 9.01 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:26 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186767244 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1186767244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1402292241 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 108196256 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402292241 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1402292241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3342405443 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 119198449 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 207664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3342405443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.3342405443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.3062492140 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 62191593 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:17 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062492140 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3062492140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.54169318 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 96913606 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54169318 -assert nopostproc +UV M_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.54169318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2362698584 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 97732293 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 217444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362698584 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2362698584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2549133606 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 516283502 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 08:31:13 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 207548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549133606 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.2549133606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.451557039 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 430361125 ps |
| CPU time | 2.31 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451557039 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.451557039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2609489048 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 492117615 ps |
| CPU time | 5.49 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609489048 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2609489048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.110930396 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 96105923 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110930396 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.110930396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1495749111 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 141204898 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1495749111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.1495749111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3822027384 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 62036538 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822027384 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3822027384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1023458863 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 115616621 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023458863 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.1023458863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.401212710 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 587367663 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401212710 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.401212710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.355529496 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 357197298 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355529496 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.355529496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1558086907 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 493165282 ps |
| CPU time | 5.18 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:44 PM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558086907 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1558086907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3323952378 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 109248784 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323952378 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3323952378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1028966657 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 102817321 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1028966657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.1028966657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3566258536 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 61737302 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566258536 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3566258536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4048337643 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 158497603 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048337643 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.4048337643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.4095833176 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 317273886 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095833176 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4095833176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1978651356 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 564528621 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 08:31:15 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978651356 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.1978651356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3717281103 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 197662348 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:31:17 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3717281103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.3717281103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2042081315 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 74992043 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042081315 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2042081315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.867819705 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 139864867 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867819705 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.867819705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.409928760 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 190065888 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409928760 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.409928760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3236871359 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 487284464 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 08:31:16 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236871359 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.3236871359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1564944103 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 113497789 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1564944103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.1564944103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2286639776 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 72325106 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:31:18 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286639776 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2286639776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2447162950 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 243000483 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 08:31:18 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447162950 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.2447162950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2594850614 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 341115756 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 08:31:18 PM UTC 24 |
| Finished | Sep 01 08:31:42 PM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594850614 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2594850614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3666810454 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 195113826 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:33 PM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3666810454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.3666810454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.2265903832 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 69111759 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265903832 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2265903832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2603685330 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 221497867 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603685330 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.2603685330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.2025419805 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 123486904 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025419805 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2025419805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1046927690 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 138531280 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:31:20 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1046927690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.1046927690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.566013917 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 75231929 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566013917 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.566013917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2435528724 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 100366020 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435528724 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.2435528724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.40344236 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 167902097 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:34 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40344236 -assert nopostproc +UVM_TESTNAME=rstmgr_bas e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.40344236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2022785140 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 444952956 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 08:31:19 PM UTC 24 |
| Finished | Sep 01 08:31:33 PM UTC 24 |
| Peak memory | 207444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022785140 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.2022785140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2541642821 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 115789674 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:31:24 PM UTC 24 |
| Finished | Sep 01 08:31:39 PM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2541642821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.2541642821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.852046198 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 71649247 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:31:22 PM UTC 24 |
| Finished | Sep 01 08:31:38 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852046198 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.852046198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2240492149 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 234911625 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:31:23 PM UTC 24 |
| Finished | Sep 01 08:31:41 PM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240492149 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.2240492149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.182929484 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 446615698 ps |
| CPU time | 3 seconds |
| Started | Sep 01 08:31:21 PM UTC 24 |
| Finished | Sep 01 08:31:43 PM UTC 24 |
| Peak memory | 225132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182929484 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.182929484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3772687619 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 522111823 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 08:31:22 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772687619 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.3772687619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.186553645 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 301487716 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186553645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.186553645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1437967119 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1336087155 ps |
| CPU time | 4.81 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:21 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437967119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1437967119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.3645423401 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8459887845 ps |
| CPU time | 11.34 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:28 PM UTC 24 |
| Peak memory | 241856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645423401 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3645423401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3050014105 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 378486075 ps |
| CPU time | 2.26 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:18 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050014105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3050014105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1135586328 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 168530798 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135586328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1135586328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.2315222987 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 65163481 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:27 PM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315222987 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2315222987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.644516726 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1951879993 ps |
| CPU time | 7.04 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:33 PM UTC 24 |
| Peak memory | 241952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644516726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.644516726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.196810115 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 305707996 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:27 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196810115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.196810115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3631784798 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 85647038 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:17 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631784798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3631784798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1738747371 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1698883900 ps |
| CPU time | 5.26 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:32 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738747371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1738747371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2969990535 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 112244642 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:27 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969990535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2969990535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.1742275399 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1215167700 ps |
| CPU time | 5.32 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:32 PM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742275399 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1742275399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2456622905 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 150618903 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:28 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456622905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2456622905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1763135855 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 176694146 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:27 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763135855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1763135855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.621724428 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 90699190 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621724428 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.621724428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.112630352 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2465836963 ps |
| CPU time | 8.03 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:51 PM UTC 24 |
| Peak memory | 242452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112630352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.112630352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.920574086 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 301692234 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920574086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.920574086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.918443615 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 112704563 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:43 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918443615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.918443615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.4224256553 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 861499117 ps |
| CPU time | 4.45 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224256553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4224256553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1537918596 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 95112332 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537918596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1537918596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.1345971653 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 191359249 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345971653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1345971653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.1529048464 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 9537116443 ps |
| CPU time | 30.63 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:30:14 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529048464 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1529048464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.1993921162 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 539752346 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993921162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1993921162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.955160667 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 136782669 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:43 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955160667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.955160667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.536017768 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 83902748 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536017768 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.536017768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.3595531540 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2432137294 ps |
| CPU time | 7.72 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:51 PM UTC 24 |
| Peak memory | 242452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595531540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3595531540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2860443270 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 301698759 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860443270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2860443270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3292046659 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 135566585 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292046659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3292046659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3883509005 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1224325776 ps |
| CPU time | 5.05 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883509005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3883509005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.258602078 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 171245006 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258602078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.258602078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.2557035704 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 233193793 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557035704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2557035704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.144504273 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2452718027 ps |
| CPU time | 9.98 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144504273 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.144504273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.3662517628 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 136526084 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662517628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3662517628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2422574960 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 87232397 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422574960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2422574960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3917984108 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 67162925 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:29:44 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917984108 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3917984108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.2794309810 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1274037745 ps |
| CPU time | 5.33 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:49 PM UTC 24 |
| Peak memory | 241672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794309810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2794309810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2815477983 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 302616874 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:29:44 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815477983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2815477983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.1414177390 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 125748465 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414177390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1414177390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.1233525074 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 815205637 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233525074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1233525074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2295538543 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 100690636 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295538543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2295538543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3774698194 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 113441517 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774698194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3774698194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.205348488 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2650430561 ps |
| CPU time | 8.29 seconds |
| Started | Sep 01 08:29:44 PM UTC 24 |
| Finished | Sep 01 08:29:54 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205348488 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.205348488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.985304 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 317914182 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 208004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rs tmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.985304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2963098707 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 199652739 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 08:29:42 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963098707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2963098707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.518074253 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 87029191 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518074253 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.518074253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3169008137 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1972499777 ps |
| CPU time | 7.47 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:54 PM UTC 24 |
| Peak memory | 241660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169008137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3169008137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1147551184 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 302576175 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147551184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1147551184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2801587416 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 126775472 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801587416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2801587416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.3891817312 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1116290278 ps |
| CPU time | 5.33 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:52 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891817312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3891817312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1956409564 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 178944844 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 208020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956409564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1956409564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.997235974 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 192362521 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:29:44 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997235974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.997235974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1245051199 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4228739405 ps |
| CPU time | 17.18 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:30:04 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245051199 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1245051199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.2163173685 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 121827856 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163173685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2163173685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.4146591907 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 130899821 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146591907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4146591907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1103371418 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 90159486 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:29:47 PM UTC 24 |
| Finished | Sep 01 08:29:52 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103371418 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1103371418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.3091930577 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2257834533 ps |
| CPU time | 7.35 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:54 PM UTC 24 |
| Peak memory | 241488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091930577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3091930577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2970759903 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 302371590 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970759903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2970759903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.832824350 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 195118551 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832824350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.832824350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1619087304 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1613509985 ps |
| CPU time | 5.53 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619087304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1619087304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2965448585 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 101994796 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965448585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2965448585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3710531598 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 185694139 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710531598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3710531598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.318196677 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 217332511 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318196677 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.318196677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.3591382658 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 133914985 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 216860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591382658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3591382658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.3410141222 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 84496116 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:29:45 PM UTC 24 |
| Finished | Sep 01 08:29:48 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410141222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3410141222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.576316852 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 68204933 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576316852 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.576316852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.108083204 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2453346248 ps |
| CPU time | 7.41 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108083204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.108083204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3506951932 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 302193566 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:29:57 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506951932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3506951932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3303320002 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 76325544 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:29:47 PM UTC 24 |
| Finished | Sep 01 08:29:52 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303320002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3303320002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.2304866677 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 817212646 ps |
| CPU time | 3.68 seconds |
| Started | Sep 01 08:29:47 PM UTC 24 |
| Finished | Sep 01 08:29:59 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304866677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2304866677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4093173013 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 111529138 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093173013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4093173013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.758064166 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 120327534 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:29:47 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758064166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.758064166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.922601720 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2034515278 ps |
| CPU time | 8.41 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922601720 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.922601720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.144461789 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 314660212 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:29:58 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144461789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.144461789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.112030508 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 122987446 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:29:57 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112030508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.112030508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.866392822 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 57993059 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:29:49 PM UTC 24 |
| Finished | Sep 01 08:29:52 PM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866392822 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.866392822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.3987535786 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2462596817 ps |
| CPU time | 8.91 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 241636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987535786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3987535786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4157236884 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 302332802 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 237404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157236884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4157236884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.3755295188 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 188957341 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755295188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3755295188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.825068782 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 941077777 ps |
| CPU time | 4.01 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:06 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825068782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.825068782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1852602627 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 174205284 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852602627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1852602627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3952768478 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 250609920 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:04 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952768478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3952768478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.4139560048 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4951122015 ps |
| CPU time | 17.06 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:24 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139560048 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4139560048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.3122544718 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 436785512 ps |
| CPU time | 2.26 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:05 PM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122544718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3122544718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3028286750 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 231446341 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:29:48 PM UTC 24 |
| Finished | Sep 01 08:30:04 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028286750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3028286750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.1493117357 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 64496299 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493117357 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1493117357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.1288817018 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1963000858 ps |
| CPU time | 7.26 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 242056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288817018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1288817018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2942240739 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 302333324 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942240739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2942240739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1730397523 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 214577445 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:29:50 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 208168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730397523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1730397523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.1943780473 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1459368497 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 08:29:50 PM UTC 24 |
| Finished | Sep 01 08:29:57 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943780473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1943780473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3719683979 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 182279332 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719683979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3719683979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.1484342948 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 194487671 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:29:49 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484342948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1484342948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.155593053 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6597674082 ps |
| CPU time | 20.03 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:22 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155593053 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.155593053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.3680412325 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 392285713 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:29:54 PM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680412325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3680412325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.701321719 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 102575507 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:29:50 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 207992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701321719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.701321719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.2098985215 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 74658235 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:29:52 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098985215 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2098985215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.1766834107 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2430626689 ps |
| CPU time | 8.95 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 241704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766834107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1766834107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4193571865 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 301745596 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:04 PM UTC 24 |
| Peak memory | 237524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193571865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4193571865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.916043759 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 185447912 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916043759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.916043759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1426436869 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1982208685 ps |
| CPU time | 7.26 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426436869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1426436869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.431449700 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 104025635 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 206384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431449700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.431449700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.3102440049 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 203945952 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102440049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3102440049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.1508216723 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 320411496 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 08:29:52 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 207964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508216723 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1508216723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.3075362522 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 328909948 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:04 PM UTC 24 |
| Peak memory | 216660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075362522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3075362522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.2974434251 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 223163151 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:29:51 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974434251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2974434251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.2621455961 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 81324313 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621455961 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2621455961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.2405877238 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1964134122 ps |
| CPU time | 6.99 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 241416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405877238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2405877238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3133395789 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 301327720 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 237264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133395789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3133395789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.3121740380 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 86532370 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:29:52 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121740380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3121740380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.3576632503 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1946591982 ps |
| CPU time | 6.24 seconds |
| Started | Sep 01 08:29:52 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576632503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3576632503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.187028935 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 101113459 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187028935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.187028935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.544871176 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 117994101 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:29:52 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544871176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.544871176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.2972112469 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4828529885 ps |
| CPU time | 19.55 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:26 PM UTC 24 |
| Peak memory | 209104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972112469 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2972112469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3385761686 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 124697610 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385761686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3385761686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.209090350 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 120321161 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:29:52 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209090350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.209090350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.3855878309 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 70913142 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855878309 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3855878309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1906240050 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 301492389 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:18 PM UTC 24 |
| Peak memory | 237620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906240050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1906240050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3963845315 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 181494999 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963845315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3963845315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1023315394 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1474544212 ps |
| CPU time | 5.02 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:42 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023315394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1023315394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.2747240359 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 16520702297 ps |
| CPU time | 29.41 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 241496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747240359 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2747240359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1927164051 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 156206297 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927164051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1927164051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.3115019030 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 267082711 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:28 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115019030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3115019030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.846075488 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 6711169454 ps |
| CPU time | 26 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846075488 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.846075488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2090925531 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 197901899 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:29:12 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 206340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090925531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2090925531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3497479155 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 70946964 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:29:57 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 207972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497479155 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3497479155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.1414062174 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1959380432 ps |
| CPU time | 7.23 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:15 PM UTC 24 |
| Peak memory | 241976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414062174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1414062174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.180419504 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 302533172 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180419504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.180419504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.1356009672 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 155158100 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356009672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1356009672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.3608495524 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 640651059 ps |
| CPU time | 3.49 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:10 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608495524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3608495524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3317410967 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 103775354 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317410967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3317410967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.817843949 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 235026572 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:29:54 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817843949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.817843949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.1122554280 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 7205387140 ps |
| CPU time | 30.32 seconds |
| Started | Sep 01 08:29:57 PM UTC 24 |
| Finished | Sep 01 08:30:39 PM UTC 24 |
| Peak memory | 220156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122554280 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1122554280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.819652285 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 138329319 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819652285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.819652285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3394287812 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 84534102 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:29:55 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394287812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3394287812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.994417803 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 71916030 ps |
| CPU time | 0.73 seconds |
| Started | Sep 01 08:30:03 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994417803 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.994417803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.1272809476 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2454310423 ps |
| CPU time | 8.24 seconds |
| Started | Sep 01 08:30:01 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 242404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272809476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1272809476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2726497348 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 301823114 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:30:03 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 237680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726497348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2726497348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.1883623212 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 142616701 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:29:57 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883623212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1883623212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.292330393 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 694166269 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 08:29:59 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292330393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.292330393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.909854615 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 181410533 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:29:59 PM UTC 24 |
| Finished | Sep 01 08:30:02 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909854615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.909854615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.1010253013 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 121497456 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:29:57 PM UTC 24 |
| Finished | Sep 01 08:30:10 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010253013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1010253013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.883823873 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7349259834 ps |
| CPU time | 23.84 seconds |
| Started | Sep 01 08:30:03 PM UTC 24 |
| Finished | Sep 01 08:30:32 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883823873 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.883823873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.781275171 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 140360687 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:29:59 PM UTC 24 |
| Finished | Sep 01 08:30:03 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781275171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.781275171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.2722416644 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 83123901 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:29:59 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722416644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2722416644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1128956866 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 67612041 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128956866 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1128956866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3122610683 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1271997130 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 241728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122610683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3122610683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4229091957 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 301322582 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 237196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229091957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4229091957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.756263140 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 179369673 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:30:04 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756263140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.756263140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.826214527 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1582923568 ps |
| CPU time | 5.83 seconds |
| Started | Sep 01 08:30:04 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826214527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.826214527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2328525475 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 171201440 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328525475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2328525475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2106740372 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 124817437 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:30:04 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106740372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2106740372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.1832282349 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2613009287 ps |
| CPU time | 9.24 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:17 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832282349 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1832282349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.2400025957 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 502040015 ps |
| CPU time | 2.72 seconds |
| Started | Sep 01 08:30:04 PM UTC 24 |
| Finished | Sep 01 08:30:10 PM UTC 24 |
| Peak memory | 208988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400025957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2400025957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.2453895398 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 73532584 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:30:04 PM UTC 24 |
| Finished | Sep 01 08:30:07 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453895398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2453895398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.882357511 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 58321978 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:30:07 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882357511 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.882357511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.2627527282 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1275996136 ps |
| CPU time | 5.27 seconds |
| Started | Sep 01 08:30:06 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 242300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627527282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2627527282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.692483222 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 301368519 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:30:06 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 237452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692483222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.692483222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3242535279 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 206404758 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242535279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3242535279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.3673751595 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2021670541 ps |
| CPU time | 6.77 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:14 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673751595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3673751595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3390820893 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 105701882 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:30:06 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390820893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3390820893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.316575832 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 113277282 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316575832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.316575832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.3192020196 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 11508253410 ps |
| CPU time | 39.88 seconds |
| Started | Sep 01 08:30:07 PM UTC 24 |
| Finished | Sep 01 08:30:48 PM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192020196 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3192020196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.2580925431 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 136952949 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:09 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580925431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2580925431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.1083722250 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 217855983 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:30:05 PM UTC 24 |
| Finished | Sep 01 08:30:08 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083722250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1083722250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.1901602264 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 67581499 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901602264 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1901602264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.1568459768 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1268454890 ps |
| CPU time | 5.54 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:15 PM UTC 24 |
| Peak memory | 241596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568459768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1568459768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1492606194 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 302317565 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492606194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1492606194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.473607969 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 182375507 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:10 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473607969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.473607969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.3042326376 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1612667682 ps |
| CPU time | 6.44 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:16 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042326376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3042326376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3065970910 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 140317359 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065970910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3065970910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.2473049559 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 188318881 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:30:07 PM UTC 24 |
| Finished | Sep 01 08:30:10 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473049559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2473049559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3719958403 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 119581188 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719958403 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3719958403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.434640988 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 295571866 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:12 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434640988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.434640988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.749703079 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 100240555 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:30:08 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749703079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.749703079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3064591817 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 77568494 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064591817 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3064591817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.3180919790 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1955204852 ps |
| CPU time | 7.77 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 241888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180919790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3180919790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1965482002 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 301867104 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965482002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1965482002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.976046150 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 87942867 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976046150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.976046150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.1088043674 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 780376796 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:14 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088043674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1088043674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3005580656 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 97027924 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005580656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3005580656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.2938361771 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 112568119 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938361771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2938361771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.1555167514 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2783501671 ps |
| CPU time | 10.2 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:22 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555167514 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1555167514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3799447392 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 351868766 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799447392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3799447392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3945151116 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 225749477 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:30:09 PM UTC 24 |
| Finished | Sep 01 08:30:11 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945151116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3945151116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2512462557 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 66082709 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512462557 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2512462557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2767689430 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1968597359 ps |
| CPU time | 8.19 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:20 PM UTC 24 |
| Peak memory | 242364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767689430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2767689430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2372843511 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 302030243 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372843511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2372843511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.3034997462 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 136191407 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:12 PM UTC 24 |
| Peak memory | 208168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034997462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3034997462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.2823555685 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 877821062 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:16 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823555685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2823555685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2013996157 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 183989310 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013996157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2013996157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.3366470575 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 108279400 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366470575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3366470575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.3253974542 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4748395856 ps |
| CPU time | 18.51 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:31 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253974542 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3253974542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.4041556336 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 352324449 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:14 PM UTC 24 |
| Peak memory | 209060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041556336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4041556336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3762834270 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 134200250 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762834270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3762834270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.2028976605 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 76038428 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028976605 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2028976605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.15394327 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2435223832 ps |
| CPU time | 8.06 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:20 PM UTC 24 |
| Peak memory | 242312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15394327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.15394327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3561047903 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 305625948 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 237196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561047903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3561047903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.4109805183 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 181783667 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109805183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4109805183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.1103508695 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1435922389 ps |
| CPU time | 5.27 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:17 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103508695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1103508695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2767609057 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 98151678 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767609057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2767609057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.2029720256 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 199743778 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 08:30:10 PM UTC 24 |
| Finished | Sep 01 08:30:14 PM UTC 24 |
| Peak memory | 208228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029720256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2029720256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.1571723860 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1119289542 ps |
| CPU time | 5.5 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 219900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571723860 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1571723860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.4075464995 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 146493070 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:14 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075464995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4075464995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.1334062453 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 169399679 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:30:11 PM UTC 24 |
| Finished | Sep 01 08:30:13 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334062453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1334062453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.823917680 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 62954657 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823917680 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.823917680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.3349176960 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1273121646 ps |
| CPU time | 5.39 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:22 PM UTC 24 |
| Peak memory | 241400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349176960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3349176960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3100877494 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 301452831 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 235720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100877494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3100877494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.902323385 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 146946721 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:17 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902323385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.902323385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.862759778 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1829461523 ps |
| CPU time | 6.95 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862759778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.862759778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1297928071 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 153191346 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297928071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1297928071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.1065636190 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 202404175 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065636190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1065636190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.3998864185 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 10731242181 ps |
| CPU time | 37.26 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:54 PM UTC 24 |
| Peak memory | 209080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998864185 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3998864185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.1273887566 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 501378059 ps |
| CPU time | 3.16 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:20 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273887566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1273887566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.1889411281 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 116288607 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889411281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1889411281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.940408137 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 226828060 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:30:13 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940408137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.940408137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.3178353715 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1084960878 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 08:30:13 PM UTC 24 |
| Finished | Sep 01 08:30:22 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178353715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3178353715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.4189652036 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 197069282 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 08:30:12 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189652036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4189652036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.1623759486 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 9803533217 ps |
| CPU time | 28.96 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:45 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623759486 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1623759486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.3267842124 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 126903238 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 08:30:13 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267842124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3267842124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.2205230081 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 72204124 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:30:13 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 207960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205230081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2205230081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1219687736 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 64397487 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 207996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219687736 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1219687736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.786954592 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2443381404 ps |
| CPU time | 8.34 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:46 PM UTC 24 |
| Peak memory | 241736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786954592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.786954592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.154161878 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 301993421 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154161878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.154161878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.9929544 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 94373185 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9929544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.9929544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.2418651523 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 809005207 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418651523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2418651523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.94702433 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8986184871 ps |
| CPU time | 12.71 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:50 PM UTC 24 |
| Peak memory | 241808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94702433 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.94702433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2712922796 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 96815027 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712922796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2712922796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1205644197 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 196692447 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205644197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1205644197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3933265464 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 129909517 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933265464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3933265464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2105616261 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 223115488 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105616261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2105616261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.3192122957 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 95658341 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192122957 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3192122957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.2821618737 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2268380457 ps |
| CPU time | 7.98 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:24 PM UTC 24 |
| Peak memory | 241720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821618737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2821618737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2521416320 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 301908938 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521416320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2521416320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.4115381321 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1427997801 ps |
| CPU time | 5.71 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:22 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115381321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4115381321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1842015760 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 150863653 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842015760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1842015760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.1098359619 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4388058158 ps |
| CPU time | 18.78 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:36 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098359619 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1098359619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.325512258 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 438071313 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 209000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325512258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.325512258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3579559308 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 145780257 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579559308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3579559308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.3544654908 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 81992065 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544654908 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3544654908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.1417142803 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1956292166 ps |
| CPU time | 7.57 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:25 PM UTC 24 |
| Peak memory | 242404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417142803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1417142803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1738174123 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 302107436 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 237532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738174123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1738174123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.3555714138 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 166617256 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555714138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3555714138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.3586814459 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 810747123 ps |
| CPU time | 4.33 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:21 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586814459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3586814459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1916694742 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 168315797 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916694742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1916694742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.373746552 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 122407831 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373746552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.373746552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.2289063364 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 312946275 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 209180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289063364 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2289063364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.3527978158 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 357072473 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:20 PM UTC 24 |
| Peak memory | 209056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527978158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3527978158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.1667128034 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 161949062 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:30:14 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667128034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1667128034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.832822294 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 58440066 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832822294 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.832822294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2426622970 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 302080226 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:30:18 PM UTC 24 |
| Finished | Sep 01 08:30:27 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426622970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2426622970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.2231576116 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 152247395 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:18 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231576116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2231576116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.2069505819 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1885381806 ps |
| CPU time | 5.91 seconds |
| Started | Sep 01 08:30:17 PM UTC 24 |
| Finished | Sep 01 08:30:27 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069505819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2069505819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.157623637 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 201745104 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 08:30:16 PM UTC 24 |
| Finished | Sep 01 08:30:19 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157623637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.157623637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.1020817011 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 10628997821 ps |
| CPU time | 31.45 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:54 PM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020817011 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1020817011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.688267449 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 105495260 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:30:17 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688267449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.688267449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.3729219181 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 89189497 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:30:20 PM UTC 24 |
| Finished | Sep 01 08:30:22 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729219181 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3729219181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.661216723 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1960623217 ps |
| CPU time | 6.4 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:28 PM UTC 24 |
| Peak memory | 241664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661216723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.661216723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.3041744175 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 175318567 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041744175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3041744175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.566832830 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1013920404 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:27 PM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566832830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.566832830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3498499803 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 169534938 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498499803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3498499803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.3569022683 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 203706407 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569022683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3569022683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.111360204 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 335119393 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:24 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111360204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.111360204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.1360926998 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 113622712 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:30:19 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 208292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360926998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1360926998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1546961292 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 177899764 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 08:30:20 PM UTC 24 |
| Finished | Sep 01 08:30:23 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546961292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1546961292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.3269504067 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 81948812 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:30:22 PM UTC 24 |
| Finished | Sep 01 08:30:27 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269504067 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3269504067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.3590070542 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2419207818 ps |
| CPU time | 7.6 seconds |
| Started | Sep 01 08:30:21 PM UTC 24 |
| Finished | Sep 01 08:31:17 PM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590070542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3590070542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1993129601 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 302031348 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:30:21 PM UTC 24 |
| Finished | Sep 01 08:31:11 PM UTC 24 |
| Peak memory | 237456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993129601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1993129601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3413267176 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 96067116 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:30:21 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413267176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3413267176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.4055328091 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2031335271 ps |
| CPU time | 6.93 seconds |
| Started | Sep 01 08:30:22 PM UTC 24 |
| Finished | Sep 01 08:30:33 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055328091 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.4055328091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.673966928 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 354736097 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 08:30:21 PM UTC 24 |
| Finished | Sep 01 08:31:11 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673966928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.673966928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.1415941070 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 189200361 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:30:21 PM UTC 24 |
| Finished | Sep 01 08:31:11 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415941070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1415941070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.865843056 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 72063109 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:30:25 PM UTC 24 |
| Finished | Sep 01 08:30:38 PM UTC 24 |
| Peak memory | 207804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865843056 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.865843056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.742041439 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1265092282 ps |
| CPU time | 5.11 seconds |
| Started | Sep 01 08:30:24 PM UTC 24 |
| Finished | Sep 01 08:31:07 PM UTC 24 |
| Peak memory | 242408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742041439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.742041439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3921717791 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 301951249 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:30:24 PM UTC 24 |
| Finished | Sep 01 08:31:03 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921717791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3921717791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.3846194348 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 148781041 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:30:22 PM UTC 24 |
| Finished | Sep 01 08:30:38 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846194348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3846194348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1835098953 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1510623180 ps |
| CPU time | 5.58 seconds |
| Started | Sep 01 08:30:22 PM UTC 24 |
| Finished | Sep 01 08:30:43 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835098953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1835098953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.843114387 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 143111405 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:30:24 PM UTC 24 |
| Finished | Sep 01 08:30:42 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843114387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.843114387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.2583232988 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 111358003 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:30:22 PM UTC 24 |
| Finished | Sep 01 08:30:28 PM UTC 24 |
| Peak memory | 208276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583232988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2583232988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.1704174765 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 10075160021 ps |
| CPU time | 33.42 seconds |
| Started | Sep 01 08:30:24 PM UTC 24 |
| Finished | Sep 01 08:31:36 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704174765 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1704174765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.829679978 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 409489411 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 08:30:24 PM UTC 24 |
| Finished | Sep 01 08:31:04 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829679978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.829679978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.2081622449 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 121740226 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:30:24 PM UTC 24 |
| Finished | Sep 01 08:30:42 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081622449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2081622449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.1218221787 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 77660459 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:30:28 PM UTC 24 |
| Finished | Sep 01 08:30:37 PM UTC 24 |
| Peak memory | 207996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218221787 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1218221787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.1814529482 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1276504686 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 08:30:27 PM UTC 24 |
| Finished | Sep 01 08:30:46 PM UTC 24 |
| Peak memory | 242164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814529482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1814529482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2602870402 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 301625790 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:30:27 PM UTC 24 |
| Finished | Sep 01 08:30:42 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602870402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2602870402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.1205465966 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 164900029 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:30:25 PM UTC 24 |
| Finished | Sep 01 08:30:38 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205465966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1205465966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.2400684151 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 906363675 ps |
| CPU time | 3.99 seconds |
| Started | Sep 01 08:30:25 PM UTC 24 |
| Finished | Sep 01 08:30:41 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400684151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2400684151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3370352016 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 149320052 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:30:26 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 208376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370352016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3370352016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.194851231 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 243909389 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 08:30:25 PM UTC 24 |
| Finished | Sep 01 08:30:39 PM UTC 24 |
| Peak memory | 207912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194851231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.194851231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3522447569 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 7352134888 ps |
| CPU time | 29.07 seconds |
| Started | Sep 01 08:30:28 PM UTC 24 |
| Finished | Sep 01 08:31:06 PM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522447569 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3522447569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.178322829 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 137529510 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 08:30:26 PM UTC 24 |
| Finished | Sep 01 08:30:39 PM UTC 24 |
| Peak memory | 207620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178322829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.178322829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.3638658023 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 270709292 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 08:30:25 PM UTC 24 |
| Finished | Sep 01 08:30:39 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638658023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3638658023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1400911533 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 67993171 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:30:48 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400911533 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1400911533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.3620649616 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1267463368 ps |
| CPU time | 5.08 seconds |
| Started | Sep 01 08:30:37 PM UTC 24 |
| Finished | Sep 01 08:30:46 PM UTC 24 |
| Peak memory | 242036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620649616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3620649616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4247164770 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 301746484 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:30:48 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247164770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4247164770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.661001969 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 217366973 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:30:28 PM UTC 24 |
| Finished | Sep 01 08:30:38 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661001969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.661001969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.3972816841 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 880909155 ps |
| CPU time | 4.09 seconds |
| Started | Sep 01 08:30:29 PM UTC 24 |
| Finished | Sep 01 08:30:45 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972816841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3972816841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.728288265 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 145991735 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:30:35 PM UTC 24 |
| Finished | Sep 01 08:30:38 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728288265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.728288265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.1675609512 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 193833208 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:30:28 PM UTC 24 |
| Finished | Sep 01 08:30:38 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675609512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1675609512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.177505663 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3821511670 ps |
| CPU time | 11.43 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:30:58 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177505663 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.177505663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.4228603054 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 394649347 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 08:30:32 PM UTC 24 |
| Finished | Sep 01 08:30:39 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228603054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4228603054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.2314457863 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 100985413 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:30:31 PM UTC 24 |
| Finished | Sep 01 08:31:06 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314457863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2314457863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.339435212 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 80905417 ps |
| CPU time | 0.69 seconds |
| Started | Sep 01 08:30:42 PM UTC 24 |
| Finished | Sep 01 08:30:47 PM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339435212 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.339435212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1181437907 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2273596375 ps |
| CPU time | 8.11 seconds |
| Started | Sep 01 08:30:40 PM UTC 24 |
| Finished | Sep 01 08:31:17 PM UTC 24 |
| Peak memory | 242460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181437907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1181437907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3310219908 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 301744144 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:30:40 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 237456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310219908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3310219908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.227332750 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 132406321 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227332750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.227332750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.3052844427 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 874171176 ps |
| CPU time | 4.21 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:31:11 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052844427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3052844427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1097007957 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 140865874 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:30:40 PM UTC 24 |
| Finished | Sep 01 08:31:03 PM UTC 24 |
| Peak memory | 208376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097007957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1097007957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.2398203539 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 117021802 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398203539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2398203539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.2696033730 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 309660604 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 08:30:40 PM UTC 24 |
| Finished | Sep 01 08:30:43 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696033730 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2696033730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.3280350444 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 397696920 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 08:30:40 PM UTC 24 |
| Finished | Sep 01 08:31:04 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280350444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3280350444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.2821694545 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 164608789 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:30:39 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 208208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821694545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2821694545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.2558668465 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 74272454 ps |
| CPU time | 0.74 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558668465 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2558668465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2829727195 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 301944221 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 237620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829727195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2829727195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.2088870683 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 168320268 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088870683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2088870683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.3819110806 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1942293629 ps |
| CPU time | 6.54 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819110806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3819110806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.3413289392 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 8289889632 ps |
| CPU time | 13.49 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:52 PM UTC 24 |
| Peak memory | 241792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413289392 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3413289392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3917614304 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 144781340 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917614304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3917614304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.612294989 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 114693692 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:29:13 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612294989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.612294989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.1933955066 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3398183595 ps |
| CPU time | 11.83 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:50 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933955066 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1933955066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.2509688415 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 464329103 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509688415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2509688415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.3186900302 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 91247862 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:30:48 PM UTC 24 |
| Finished | Sep 01 08:31:02 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186900302 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3186900302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.2114887356 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1267121676 ps |
| CPU time | 5.14 seconds |
| Started | Sep 01 08:30:46 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 241940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114887356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2114887356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1378912395 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 301149505 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:30:47 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378912395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1378912395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.1503260913 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 134403258 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:30:43 PM UTC 24 |
| Finished | Sep 01 08:31:02 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503260913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1503260913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2520562356 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1450576521 ps |
| CPU time | 5.08 seconds |
| Started | Sep 01 08:30:43 PM UTC 24 |
| Finished | Sep 01 08:31:07 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520562356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2520562356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3816285800 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 105033599 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:30:45 PM UTC 24 |
| Finished | Sep 01 08:30:47 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816285800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3816285800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.286810558 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 128359321 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:30:42 PM UTC 24 |
| Finished | Sep 01 08:30:47 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286810558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.286810558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.859230927 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4164989576 ps |
| CPU time | 17.26 seconds |
| Started | Sep 01 08:30:48 PM UTC 24 |
| Finished | Sep 01 08:31:19 PM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859230927 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.859230927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.2931728845 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 341941460 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 08:30:43 PM UTC 24 |
| Finished | Sep 01 08:31:03 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931728845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2931728845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.234501335 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 103289641 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:30:43 PM UTC 24 |
| Finished | Sep 01 08:31:02 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234501335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.234501335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.4240412480 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 65736909 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:30:59 PM UTC 24 |
| Finished | Sep 01 08:31:02 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240412480 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4240412480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.4029463535 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1963585289 ps |
| CPU time | 6.55 seconds |
| Started | Sep 01 08:30:54 PM UTC 24 |
| Finished | Sep 01 08:31:03 PM UTC 24 |
| Peak memory | 242400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029463535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4029463535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1752667352 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 301990332 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:30:55 PM UTC 24 |
| Finished | Sep 01 08:30:57 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752667352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1752667352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.1662284332 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 229900115 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:30:49 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662284332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1662284332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.3522201662 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1421551269 ps |
| CPU time | 5.5 seconds |
| Started | Sep 01 08:30:49 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522201662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3522201662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1583175011 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 106734023 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:30:53 PM UTC 24 |
| Finished | Sep 01 08:31:02 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583175011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1583175011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.4096075785 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 231731364 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:30:48 PM UTC 24 |
| Finished | Sep 01 08:31:03 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096075785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4096075785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.585831215 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 8763358580 ps |
| CPU time | 25.88 seconds |
| Started | Sep 01 08:30:58 PM UTC 24 |
| Finished | Sep 01 08:31:36 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585831215 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.585831215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.3561844744 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 507899904 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 08:30:50 PM UTC 24 |
| Finished | Sep 01 08:31:05 PM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561844744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3561844744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.4044871324 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 126698740 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:30:49 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044871324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4044871324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.1915149134 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 65283226 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915149134 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1915149134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.3478998992 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2495184281 ps |
| CPU time | 8.15 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:15 PM UTC 24 |
| Peak memory | 242400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478998992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3478998992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.75074397 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 301116074 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75074397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.75074397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.4073807397 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 214363621 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:31:02 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073807397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4073807397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.2008663055 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1823785523 ps |
| CPU time | 7.69 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:15 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008663055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2008663055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3315325197 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 150863387 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315325197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3315325197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.1103054498 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 115688988 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:31:02 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 206508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103054498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1103054498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.1885127659 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3818016969 ps |
| CPU time | 17.37 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:25 PM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885127659 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1885127659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.121189817 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 460821316 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121189817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.121189817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.4033460566 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 123317992 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033460566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4033460566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.3623798568 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 81826790 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623798568 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3623798568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.2825824173 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1263157676 ps |
| CPU time | 5.74 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 241664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825824173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2825824173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.958504215 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 302870147 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 237428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958504215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.958504215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.2775767780 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 111407089 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775767780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2775767780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.3592244686 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2013633213 ps |
| CPU time | 7 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592244686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3592244686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3720328589 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 144534529 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720328589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3720328589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.1933245852 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 116158731 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933245852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1933245852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.620923341 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 9481056790 ps |
| CPU time | 29.25 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:37 PM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620923341 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.620923341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.1376046256 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 353706927 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376046256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1376046256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.1439396515 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 84829956 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439396515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1439396515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.3394688309 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 63984627 ps |
| CPU time | 0.71 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:07 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394688309 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3394688309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.3466412975 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1275008469 ps |
| CPU time | 5.15 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 242368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466412975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3466412975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1476308033 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 302993642 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476308033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1476308033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.4146504054 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 96653319 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 207796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146504054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4146504054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.4240663851 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1141122918 ps |
| CPU time | 4.54 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:11 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240663851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4240663851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.709670782 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 99075595 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:07 PM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709670782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.709670782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.1438505119 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 123274576 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:31:03 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438505119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1438505119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.2267082153 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4651902236 ps |
| CPU time | 18.24 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:25 PM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267082153 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2267082153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1015437891 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 311149576 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:09 PM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015437891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1015437891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.1968432435 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 188981084 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968432435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1968432435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.2931575077 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 56160725 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:31:08 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931575077 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2931575077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2329915238 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2223132283 ps |
| CPU time | 7.72 seconds |
| Started | Sep 01 08:31:07 PM UTC 24 |
| Finished | Sep 01 08:31:16 PM UTC 24 |
| Peak memory | 242460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329915238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2329915238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.284967841 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 301821249 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:31:08 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284967841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.284967841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.1317020948 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 198500368 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 205496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317020948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1317020948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.1053264847 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2195557588 ps |
| CPU time | 8.28 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:15 PM UTC 24 |
| Peak memory | 207692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053264847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1053264847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4094335370 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 183565496 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:31:06 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094335370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4094335370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.2391367833 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 242526404 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 08:31:04 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391367833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2391367833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2520210943 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3264307972 ps |
| CPU time | 13.31 seconds |
| Started | Sep 01 08:31:08 PM UTC 24 |
| Finished | Sep 01 08:31:22 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520210943 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2520210943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.3253542154 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 130624446 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 08:31:06 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253542154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3253542154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.77831037 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 135910186 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:31:06 PM UTC 24 |
| Finished | Sep 01 08:31:08 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77831037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.77831037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.1487217175 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 62159647 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:11 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487217175 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1487217175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.2617578792 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1962594194 ps |
| CPU time | 7.55 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:18 PM UTC 24 |
| Peak memory | 242052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617578792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2617578792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1711696069 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 301827611 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711696069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1711696069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2020152139 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 94814659 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:31:08 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020152139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2020152139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.3120365299 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 922698967 ps |
| CPU time | 4.42 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:15 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120365299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3120365299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1901258781 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 144449604 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901258781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1901258781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.282550149 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 125524160 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 08:31:08 PM UTC 24 |
| Finished | Sep 01 08:31:10 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282550149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.282550149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.3702019695 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 4754602649 ps |
| CPU time | 14.45 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:25 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702019695 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3702019695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.3139533013 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 271232067 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139533013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3139533013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.3788546074 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 273899518 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788546074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3788546074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.1220919282 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 62540421 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220919282 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1220919282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.2963372640 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1262880439 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:16 PM UTC 24 |
| Peak memory | 241708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963372640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2963372640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2692046473 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 302826083 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692046473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2692046473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.3195538138 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 132239358 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195538138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3195538138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.3439282357 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1233546163 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:16 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439282357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3439282357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.501765416 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 148280059 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501765416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.501765416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.593309393 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 228483828 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 08:31:09 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593309393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.593309393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3957918716 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3153021300 ps |
| CPU time | 13.71 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:25 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957918716 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3957918716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.4132955361 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 445448824 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 209056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132955361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4132955361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.397255550 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 229494391 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 208280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397255550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.397255550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.3289115367 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 83939702 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 207960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289115367 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3289115367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.2486502740 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1271574146 ps |
| CPU time | 5.55 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:17 PM UTC 24 |
| Peak memory | 241668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486502740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2486502740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.193317543 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 302541033 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 237452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193317543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.193317543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.1026482194 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 156697649 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:12 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026482194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1026482194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.3056921962 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 819494573 ps |
| CPU time | 4.43 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:15 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056921962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3056921962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2907923381 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 156742425 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907923381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2907923381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2413353452 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 250028741 ps |
| CPU time | 2.32 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413353452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2413353452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.214214071 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 10609245806 ps |
| CPU time | 38.91 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:51 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214214071 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.214214071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.2117349076 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 344326041 ps |
| CPU time | 2.46 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117349076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2117349076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.1824040759 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 154072155 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 08:31:10 PM UTC 24 |
| Finished | Sep 01 08:31:13 PM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824040759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1824040759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.4134260766 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 76271997 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:31:12 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134260766 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4134260766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.2977843116 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2429718039 ps |
| CPU time | 8.73 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:21 PM UTC 24 |
| Peak memory | 242468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977843116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2977843116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3726094610 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 303197971 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:31:12 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726094610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3726094610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.2043385670 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 216160967 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043385670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2043385670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.3098620374 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1361632875 ps |
| CPU time | 5.02 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:17 PM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098620374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3098620374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.37927323 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 110232539 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37927323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.37927323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.3369284752 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 126277904 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 208104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369284752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3369284752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.3233017990 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 600245109 ps |
| CPU time | 3.08 seconds |
| Started | Sep 01 08:31:12 PM UTC 24 |
| Finished | Sep 01 08:31:16 PM UTC 24 |
| Peak memory | 209052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233017990 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3233017990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.984684817 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 125941616 ps |
| CPU time | 2 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984684817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.984684817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.1919758999 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 116581600 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 08:31:11 PM UTC 24 |
| Finished | Sep 01 08:31:14 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919758999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1919758999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1371920930 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 76776088 ps |
| CPU time | 0.78 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:32 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371920930 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1371920930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.3751869182 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2455836492 ps |
| CPU time | 7.98 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 241532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751869182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3751869182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3340284060 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 301531443 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:32 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340284060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3340284060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1344287496 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 129786941 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344287496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1344287496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2234644612 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1037161486 ps |
| CPU time | 4.53 seconds |
| Started | Sep 01 08:29:19 PM UTC 24 |
| Finished | Sep 01 08:29:36 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234644612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2234644612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3045352137 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 153403584 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:32 PM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045352137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3045352137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2377792923 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 124202337 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:29:17 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377792923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2377792923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1822342921 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6667787860 ps |
| CPU time | 22.98 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:55 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822342921 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1822342921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1423920434 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 114069770 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:33 PM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423920434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1423920434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1988655346 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 88496340 ps |
| CPU time | 0.77 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:32 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988655346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1988655346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1935272959 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 80742942 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:29:28 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935272959 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1935272959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.3421846764 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1279541015 ps |
| CPU time | 6.22 seconds |
| Started | Sep 01 08:29:24 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 242384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421846764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3421846764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2086776538 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 302327481 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 08:29:28 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 237444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086776538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2086776538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.2453917570 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 88330559 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453917570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2453917570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.4182712189 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2056052747 ps |
| CPU time | 6.43 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:45 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182712189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4182712189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1330969274 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 113118146 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:29:22 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330969274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1330969274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4116829792 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 126274185 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:33 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116829792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4116829792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1840318194 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3939022714 ps |
| CPU time | 13.59 seconds |
| Started | Sep 01 08:29:28 PM UTC 24 |
| Finished | Sep 01 08:29:53 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840318194 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1840318194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.627454327 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 159951265 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 08:29:22 PM UTC 24 |
| Finished | Sep 01 08:29:42 PM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627454327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.627454327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.1979364502 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 161279278 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:29:20 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979364502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1979364502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2077184583 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 60534450 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:29:37 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077184583 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2077184583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2082601719 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2265847726 ps |
| CPU time | 7.5 seconds |
| Started | Sep 01 08:29:32 PM UTC 24 |
| Finished | Sep 01 08:29:44 PM UTC 24 |
| Peak memory | 242076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082601719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2082601719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2593612818 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 301406461 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:29:32 PM UTC 24 |
| Finished | Sep 01 08:29:37 PM UTC 24 |
| Peak memory | 237620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593612818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2593612818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.1132741784 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 154650814 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:29:28 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132741784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1132741784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3202039426 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 867753964 ps |
| CPU time | 4.29 seconds |
| Started | Sep 01 08:29:30 PM UTC 24 |
| Finished | Sep 01 08:29:43 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202039426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3202039426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.919479581 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 114657153 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:29:30 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919479581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.919479581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2485353730 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 190074072 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 08:29:28 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485353730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2485353730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.669202897 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6799286035 ps |
| CPU time | 27.11 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:30:04 PM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669202897 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.669202897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.2659561588 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 378155724 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 08:29:30 PM UTC 24 |
| Finished | Sep 01 08:29:40 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659561588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2659561588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.3675361633 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 112776078 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:29:30 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675361633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3675361633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3858314459 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 96692345 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858314459 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3858314459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.2854964444 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1280245046 ps |
| CPU time | 5.85 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:46 PM UTC 24 |
| Peak memory | 241728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854964444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2854964444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.427175084 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 301735882 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427175084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.427175084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2084443561 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 72317614 ps |
| CPU time | 0.66 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:29:37 PM UTC 24 |
| Peak memory | 205648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084443561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2084443561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1795302143 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1773832604 ps |
| CPU time | 6.42 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:29:43 PM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795302143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1795302143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2675340300 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 175155467 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:29:36 PM UTC 24 |
| Finished | Sep 01 08:29:39 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675340300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2675340300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1596828184 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 114148459 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 205740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596828184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1596828184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1638261166 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1841506305 ps |
| CPU time | 7.1 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 209160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638261166 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1638261166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.2467141428 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 146189722 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467141428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2467141428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.1419118370 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 152699191 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:29:34 PM UTC 24 |
| Finished | Sep 01 08:29:38 PM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419118370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1419118370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2966202546 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 68481661 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:43 PM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966202546 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2966202546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.762721173 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1964885123 ps |
| CPU time | 6.96 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:47 PM UTC 24 |
| Peak memory | 241928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762721173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.762721173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1023860477 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 301651715 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 237620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023860477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1023860477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.4255612078 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 179733048 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255612078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4255612078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2870381964 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 699792660 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:43 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870381964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2870381964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1968427292 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 145492997 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968427292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1968427292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.1884670872 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 124991096 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884670872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1884670872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.4118674308 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2994096877 ps |
| CPU time | 9.54 seconds |
| Started | Sep 01 08:29:41 PM UTC 24 |
| Finished | Sep 01 08:29:52 PM UTC 24 |
| Peak memory | 220156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118674308 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4118674308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4230881633 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 137204822 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:42 PM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230881633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4230881633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1559135778 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 105413927 ps |
| CPU time | 1 seconds |
| Started | Sep 01 08:29:39 PM UTC 24 |
| Finished | Sep 01 08:29:41 PM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559135778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1559135778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |