Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	635452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

381284

1

T2

6

T3

66

T4

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	543221	1			T1	1		T3	81		T4	99
values[0x0]	236554	1			T2	14		T3	48		T4	57
values[0x1]	236961	1			T2	7		T3	41		T4	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	533186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

483550

1

T2

6

T3

82

T4

93

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4062	1			T3	2		T12	2		T13	1
valid_sources[0x01]	3125	1			T3	2		T5	2		T12	1
valid_sources[0x02]	4030	1			T5	3		T63	1		T89	4
valid_sources[0x03]	3458	1			T5	4		T12	2		T13	2
valid_sources[0x04]	3358	1			T5	4		T10	1		T13	2
valid_sources[0x05]	3147	1			T3	3		T10	1		T12	3
valid_sources[0x06]	3341	1			T5	2		T13	2		T63	3
valid_sources[0x07]	7420	1			T5	1		T89	2		T91	7
valid_sources[0x08]	4061	1			T13	2		T23	1		T24	110
valid_sources[0x09]	3350	1			T5	4		T9	7		T12	2
valid_sources[0x0a]	3829	1			T13	1		T23	3		T91	4
valid_sources[0x0b]	4076	1			T5	1		T12	1		T62	19
valid_sources[0x0c]	3297	1			T5	1		T12	2		T13	4
valid_sources[0x0d]	3372	1			T3	1		T5	3		T63	3
valid_sources[0x0e]	4068	1			T3	1		T5	1		T13	1
valid_sources[0x0f]	4026	1			T9	1		T11	1		T12	1
valid_sources[0x10]	3426	1			T2	2		T12	1		T63	5
valid_sources[0x11]	4240	1			T5	1		T12	2		T13	1
valid_sources[0x12]	3040	1			T5	1		T13	2		T63	6
valid_sources[0x13]	4228	1			T3	2		T5	7		T12	2
valid_sources[0x14]	3294	1			T5	2		T12	1		T89	2
valid_sources[0x15]	3539	1			T63	1		T89	2		T91	6
valid_sources[0x16]	5316	1			T3	2		T5	1		T9	1
valid_sources[0x17]	3224	1			T3	1		T5	1		T9	4
valid_sources[0x18]	4104	1			T10	24		T12	1		T23	3
valid_sources[0x19]	3491	1			T5	1		T10	3		T13	1
valid_sources[0x1a]	4629	1			T12	3		T13	1		T63	3
valid_sources[0x1b]	4783	1			T5	1		T13	4		T63	5
valid_sources[0x1c]	3781	1			T5	3		T12	1		T63	3
valid_sources[0x1d]	4720	1			T5	4		T13	1		T23	1
valid_sources[0x1e]	4274	1			T3	8		T5	3		T13	1
valid_sources[0x1f]	5256	1			T3	2		T5	2		T62	77
valid_sources[0x20]	3666	1			T3	2		T5	2		T63	1
valid_sources[0x21]	4724	1			T3	1		T13	2		T63	3
valid_sources[0x22]	4208	1			T5	1		T13	1		T63	4
valid_sources[0x23]	3994	1			T3	1		T9	1		T13	2
valid_sources[0x24]	4170	1			T5	3		T13	1		T63	4
valid_sources[0x25]	3357	1			T5	1		T9	1		T12	1
valid_sources[0x26]	5177	1			T2	1		T3	4		T13	2
valid_sources[0x27]	4706	1			T3	3		T5	1		T10	3
valid_sources[0x28]	3269	1			T12	4		T63	4		T89	2
valid_sources[0x29]	3359	1			T5	2		T12	1		T13	2
valid_sources[0x2a]	3261	1			T3	2		T5	4		T9	1
valid_sources[0x2b]	3704	1			T5	3		T10	4		T12	1
valid_sources[0x2c]	3394	1			T5	1		T10	4		T12	6
valid_sources[0x2d]	4860	1			T5	2		T62	39		T63	1
valid_sources[0x2e]	4421	1			T2	1		T5	2		T10	2
valid_sources[0x2f]	3096	1			T3	5		T5	2		T12	1
valid_sources[0x30]	3550	1			T5	2		T12	2		T13	1
valid_sources[0x31]	3629	1			T10	6		T13	1		T63	2
valid_sources[0x32]	4459	1			T3	2		T5	2		T10	4
valid_sources[0x33]	4034	1			T3	2		T9	2		T12	7
valid_sources[0x34]	5792	1			T5	1		T12	2		T13	3
valid_sources[0x35]	7034	1			T2	1		T10	6		T12	2
valid_sources[0x36]	3364	1			T5	1		T9	2		T13	3
valid_sources[0x37]	6218	1			T3	2		T10	13		T13	2
valid_sources[0x38]	3325	1			T1	1		T5	2		T10	3
valid_sources[0x39]	3372	1			T10	7		T13	4		T63	1
valid_sources[0x3a]	3712	1			T5	2		T13	1		T63	2
valid_sources[0x3b]	3464	1			T5	2		T12	1		T13	4
valid_sources[0x3c]	4313	1			T3	4		T5	2		T9	1
valid_sources[0x3d]	3903	1			T5	1		T12	1		T23	2
valid_sources[0x3e]	3514	1			T5	2		T63	6		T89	1
valid_sources[0x3f]	4226	1			T13	1		T63	2		T23	1
valid_sources[0x40]	3502	1			T5	2		T13	1		T63	1
valid_sources[0x41]	3643	1			T13	2		T63	3		T89	3
valid_sources[0x42]	4177	1			T5	2		T63	6		T23	1
valid_sources[0x43]	4055	1			T5	2		T13	2		T63	1
valid_sources[0x44]	3542	1			T5	1		T9	2		T13	4
valid_sources[0x45]	4501	1			T5	1		T9	3		T10	1
valid_sources[0x46]	3735	1			T5	5		T9	4		T13	3
valid_sources[0x47]	3563	1			T9	2		T12	2		T62	29
valid_sources[0x48]	3116	1			T5	2		T9	3		T13	1
valid_sources[0x49]	3824	1			T5	2		T10	9		T12	1
valid_sources[0x4a]	3535	1			T5	1		T10	25		T12	1
valid_sources[0x4b]	3774	1			T5	3		T63	1		T89	5
valid_sources[0x4c]	3610	1			T3	4		T13	3		T63	3
valid_sources[0x4d]	3904	1			T13	1		T63	3		T23	1
valid_sources[0x4e]	3703	1			T5	1		T10	29		T12	1
valid_sources[0x4f]	4499	1			T5	1		T9	3		T13	3
valid_sources[0x50]	3502	1			T2	1		T3	1		T12	2
valid_sources[0x51]	4001	1			T5	1		T13	3		T23	1
valid_sources[0x52]	4361	1			T2	1		T5	2		T13	1
valid_sources[0x53]	3778	1			T3	4		T5	2		T12	2
valid_sources[0x54]	3180	1			T5	1		T12	1		T63	5
valid_sources[0x55]	4593	1			T5	1		T10	9		T13	1
valid_sources[0x56]	4869	1			T3	4		T5	1		T9	9
valid_sources[0x57]	7382	1			T5	1		T12	1		T62	156
valid_sources[0x58]	3905	1			T3	2		T5	1		T12	2
valid_sources[0x59]	3940	1			T3	2		T4	212		T5	1
valid_sources[0x5a]	4456	1			T3	2		T5	4		T10	2
valid_sources[0x5b]	3859	1			T5	1		T9	3		T10	1
valid_sources[0x5c]	3779	1			T3	3		T5	1		T12	1
valid_sources[0x5d]	3564	1			T5	1		T12	7		T13	1
valid_sources[0x5e]	3605	1			T5	4		T12	2		T13	2
valid_sources[0x5f]	3594	1			T3	1		T5	1		T12	3
valid_sources[0x60]	3291	1			T3	2		T5	1		T12	1
valid_sources[0x61]	4107	1			T3	7		T10	11		T12	1
valid_sources[0x62]	3981	1			T2	1		T23	1		T89	2
valid_sources[0x63]	3629	1			T12	1		T13	3		T63	3
valid_sources[0x64]	3695	1			T5	1		T63	5		T89	2
valid_sources[0x65]	4021	1			T5	1		T12	2		T13	2
valid_sources[0x66]	4567	1			T12	1		T62	15		T13	1
valid_sources[0x67]	3717	1			T23	1		T89	4		T88	12
valid_sources[0x68]	3348	1			T3	4		T9	2		T12	1
valid_sources[0x69]	3232	1			T5	2		T12	1		T13	4
valid_sources[0x6a]	3405	1			T10	19		T12	2		T63	3
valid_sources[0x6b]	3910	1			T9	1		T13	2		T89	5
valid_sources[0x6c]	4210	1			T13	2		T63	2		T23	1
valid_sources[0x6d]	4180	1			T5	1		T12	1		T13	2
valid_sources[0x6e]	3236	1			T5	3		T9	2		T63	10
valid_sources[0x6f]	4624	1			T3	1		T5	2		T9	2
valid_sources[0x70]	4065	1			T2	1		T13	1		T63	1
valid_sources[0x71]	3703	1			T3	1		T10	1		T12	1
valid_sources[0x72]	3307	1			T5	1		T9	1		T10	14
valid_sources[0x73]	3799	1			T3	3		T5	3		T12	1
valid_sources[0x74]	3603	1			T5	1		T12	2		T22	7
valid_sources[0x75]	3314	1			T2	1		T5	2		T12	1
valid_sources[0x76]	4283	1			T5	2		T10	1		T62	84
valid_sources[0x77]	3566	1			T2	1		T5	1		T63	3
valid_sources[0x78]	3484	1			T5	3		T9	2		T13	1
valid_sources[0x79]	5183	1			T12	1		T13	3		T63	5
valid_sources[0x7a]	4072	1			T3	2		T5	2		T9	5
valid_sources[0x7b]	3521	1			T10	3		T13	3		T63	5
valid_sources[0x7c]	3506	1			T5	1		T10	2		T12	6
valid_sources[0x7d]	4804	1			T3	2		T5	1		T9	1
valid_sources[0x7e]	4446	1			T10	14		T12	2		T13	1
valid_sources[0x7f]	3054	1			T5	2		T9	4		T13	1
valid_sources[0x80]	4320	1			T3	1		T12	1		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

254379

1

T3

38

T4

48

T5

87

values[0x0]

all_enables

biggest_size

82727

1

T2

5

T3

20

T4

20

values[0x1]

all_enables

biggest_size

44178

1

T2

1

T3

8

T4

9