Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T4,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12327417	13525	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12327417	124501	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12327417	7228970	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12327417	199097	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12327417	13525	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12327417	124501	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12327417	7228970	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12327417	199097	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	13525	0	0
T3	1783	8	0	0
T4	2302	4	0	0
T5	4480	4	0	0
T6	6985	0	0	0
T7	8871	0	0	0
T8	4638	0	0	0
T9	2052	4	0	0
T10	4364	4	0	0
T11	1962	0	0	0
T12	0	13	0	0
T13	0	4	0	0
T22	0	28	0	0
T23	0	4	0	0
T24	0	6	0	0
T25	1641	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	124501	0	0
T3	1783	72	0	0
T4	2302	37	0	0
T5	4480	38	0	0
T6	6985	0	0	0
T7	8871	0	0	0
T8	4638	0	0	0
T9	2052	38	0	0
T10	4364	38	0	0
T11	1962	0	0	0
T12	0	117	0	0
T13	0	38	0	0
T22	0	253	0	0
T23	0	37	0	0
T24	0	54	0	0
T25	1641	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7228970	0	0
T1	4855	710	0	0
T2	1794	1179	0	0
T3	1783	1025	0	0
T4	2302	1346	0	0
T5	4480	3540	0	0
T6	6985	633	0	0
T7	8871	8249	0	0
T8	4638	693	0	0
T9	2052	1109	0	0
T10	4364	3432	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	199097	0	0
T3	1783	116	0	0
T4	2302	61	0	0
T5	4480	65	0	0
T6	6985	0	0	0
T7	8871	0	0	0
T8	4638	0	0	0
T9	2052	68	0	0
T10	4364	54	0	0
T11	1962	0	0	0
T12	0	187	0	0
T13	0	78	0	0
T22	0	410	0	0
T23	0	62	0	0
T24	0	96	0	0
T25	1641	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	13525	0	0
T3	1783	8	0	0
T4	2302	4	0	0
T5	4480	4	0	0
T6	6985	0	0	0
T7	8871	0	0	0
T8	4638	0	0	0
T9	2052	4	0	0
T10	4364	4	0	0
T11	1962	0	0	0
T12	0	13	0	0
T13	0	4	0	0
T22	0	28	0	0
T23	0	4	0	0
T24	0	6	0	0
T25	1641	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	124501	0	0
T3	1783	72	0	0
T4	2302	37	0	0
T5	4480	38	0	0
T6	6985	0	0	0
T7	8871	0	0	0
T8	4638	0	0	0
T9	2052	38	0	0
T10	4364	38	0	0
T11	1962	0	0	0
T12	0	117	0	0
T13	0	38	0	0
T22	0	253	0	0
T23	0	37	0	0
T24	0	54	0	0
T25	1641	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7228970	0	0
T1	4855	710	0	0
T2	1794	1179	0	0
T3	1783	1025	0	0
T4	2302	1346	0	0
T5	4480	3540	0	0
T6	6985	633	0	0
T7	8871	8249	0	0
T8	4638	693	0	0
T9	2052	1109	0	0
T10	4364	3432	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	199097	0	0
T3	1783	116	0	0
T4	2302	61	0	0
T5	4480	65	0	0
T6	6985	0	0	0
T7	8871	0	0	0
T8	4638	0	0	0
T9	2052	68	0	0
T10	4364	54	0	0
T11	1962	0	0	0
T12	0	187	0	0
T13	0	78	0	0
T22	0	410	0	0
T23	0	62	0	0
T24	0	96	0	0
T25	1641	0	0	0