Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T4 T5 T9 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T4 T5 T9 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T4,T5,T9
1	0	Covered	T10,T22,T88

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57807276	9384	0	0
CascadeEffAonToRstPorAboveRise_A	57807276	9384	0	0
CascadeEffAonToRstPorIoAboveFall_A	55493001	9384	0	0
CascadeEffAonToRstPorIoAboveRise_A	55493001	9384	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27747553	9384	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27747553	9384	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13873411	9384	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13873411	9384	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27747404	9384	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27747404	9384	0	0
CascadeLcToLcAboveFall_A	57807276	22909	0	0
CascadeLcToLcAboveRise_A	57807276	22909	0	0
CascadeLcToLcAonAboveFall_A	1751434	22909	0	0
CascadeLcToLcAonAboveRise_A	1751434	22909	0	0
CascadeLcToLcShadowedAboveFall_A	57807276	22909	0	0
CascadeLcToLcShadowedAboveRise_A	57807276	22909	0	0
CascadePorToAonAboveFall_A	1751434	7471	0	0
CascadeSysToSysAboveFall_A	57807276	22909	0	0
CascadeSysToSysAboveRise_A	57807276	22909	0	0
ScanRstToAonRise_A	1751434	250	0	0
StablePorToAonRise_A	1751434	9384	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12327417	22909	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12327417	22909	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12327417	22909	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12327417	22909	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13873411	22909	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13873411	22909	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12327417	22909	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12327417	22909	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12327417	22909	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12327417	22909	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	9384	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	1	0	0
T4	10606	2	0	0
T5	20266	2	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	2	0	0
T10	19193	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	9384	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	1	0	0
T4	10606	2	0	0
T5	20266	2	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	2	0	0
T10	19193	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55493001	9384	0	0
T1	19689	2	0	0
T2	7350	1	0	0
T3	9408	1	0	0
T4	10185	2	0	0
T5	19455	2	0	0
T6	28744	10	0	0
T7	35657	1	0	0
T8	18820	2	0	0
T9	9743	2	0	0
T10	18424	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55493001	9384	0	0
T1	19689	2	0	0
T2	7350	1	0	0
T3	9408	1	0	0
T4	10185	2	0	0
T5	19455	2	0	0
T6	28744	10	0	0
T7	35657	1	0	0
T8	18820	2	0	0
T9	9743	2	0	0
T10	18424	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747553	9384	0	0
T1	9844	2	0	0
T2	3674	1	0	0
T3	4704	1	0	0
T4	5089	2	0	0
T5	9728	2	0	0
T6	14380	10	0	0
T7	17829	1	0	0
T8	9409	2	0	0
T9	4872	2	0	0
T10	9210	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747553	9384	0	0
T1	9844	2	0	0
T2	3674	1	0	0
T3	4704	1	0	0
T4	5089	2	0	0
T5	9728	2	0	0
T6	14380	10	0	0
T7	17829	1	0	0
T8	9409	2	0	0
T9	4872	2	0	0
T10	9210	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	9384	0	0
T1	4922	2	0	0
T2	1835	1	0	0
T3	2351	1	0	0
T4	2545	2	0	0
T5	4862	2	0	0
T6	7185	10	0	0
T7	8913	1	0	0
T8	4704	2	0	0
T9	2435	2	0	0
T10	4604	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	9384	0	0
T1	4922	2	0	0
T2	1835	1	0	0
T3	2351	1	0	0
T4	2545	2	0	0
T5	4862	2	0	0
T6	7185	10	0	0
T7	8913	1	0	0
T8	4704	2	0	0
T9	2435	2	0	0
T10	4604	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747404	9384	0	0
T1	9844	2	0	0
T2	3675	1	0	0
T3	4704	1	0	0
T4	5091	2	0	0
T5	9728	2	0	0
T6	14370	10	0	0
T7	17828	1	0	0
T8	9409	2	0	0
T9	4873	2	0	0
T10	9212	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747404	9384	0	0
T1	9844	2	0	0
T2	3675	1	0	0
T3	4704	1	0	0
T4	5091	2	0	0
T5	9728	2	0	0
T6	14370	10	0	0
T7	17828	1	0	0
T8	9409	2	0	0
T9	4873	2	0	0
T10	9212	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	22909	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	9	0	0
T4	10606	6	0	0
T5	20266	6	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	6	0	0
T10	19193	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	22909	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	9	0	0
T4	10606	6	0	0
T5	20266	6	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	6	0	0
T10	19193	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	22909	0	0
T1	614	2	0	0
T2	229	1	0	0
T3	293	9	0	0
T4	318	6	0	0
T5	607	6	0	0
T6	901	10	0	0
T7	1113	1	0	0
T8	587	2	0	0
T9	303	6	0	0
T10	574	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	22909	0	0
T1	614	2	0	0
T2	229	1	0	0
T3	293	9	0	0
T4	318	6	0	0
T5	607	6	0	0
T6	901	10	0	0
T7	1113	1	0	0
T8	587	2	0	0
T9	303	6	0	0
T10	574	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	22909	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	9	0	0
T4	10606	6	0	0
T5	20266	6	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	6	0	0
T10	19193	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	22909	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	9	0	0
T4	10606	6	0	0
T5	20266	6	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	6	0	0
T10	19193	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	7471	0	0
T1	614	21	0	0
T2	229	1	0	0
T3	293	1	0	0
T4	318	1	0	0
T5	607	1	0	0
T6	901	10	0	0
T7	1113	1	0	0
T8	587	17	0	0
T9	303	1	0	0
T10	574	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	22909	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	9	0	0
T4	10606	6	0	0
T5	20266	6	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	6	0	0
T10	19193	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57807276	22909	0	0
T1	20510	2	0	0
T2	7657	1	0	0
T3	9800	9	0	0
T4	10606	6	0	0
T5	20266	6	0	0
T6	29938	10	0	0
T7	37142	1	0	0
T8	19606	2	0	0
T9	10151	6	0	0
T10	19193	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	250	0	0
T5	607	1	0	0
T6	901	0	0	0
T7	1113	0	0	0
T8	587	0	0	0
T9	303	0	0	0
T10	574	0	0	0
T11	252	0	0	0
T12	541	0	0	0
T14	921	0	0	0
T22	0	1	0	0
T25	210	0	0	0
T38	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T96	0	1	0	0
T98	0	3	0	0
T109	0	1	0	0
T131	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	9384	0	0
T1	614	2	0	0
T2	229	1	0	0
T3	293	1	0	0
T4	318	2	0	0
T5	607	2	0	0
T6	901	10	0	0
T7	1113	1	0	0
T8	587	2	0	0
T9	303	2	0	0
T10	574	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	22909	0	0
T1	4922	2	0	0
T2	1835	1	0	0
T3	2351	9	0	0
T4	2545	6	0	0
T5	4862	6	0	0
T6	7185	10	0	0
T7	8913	1	0	0
T8	4704	2	0	0
T9	2435	6	0	0
T10	4604	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	22909	0	0
T1	4922	2	0	0
T2	1835	1	0	0
T3	2351	9	0	0
T4	2545	6	0	0
T5	4862	6	0	0
T6	7185	10	0	0
T7	8913	1	0	0
T8	4704	2	0	0
T9	2435	6	0	0
T10	4604	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	22909	0	0
T1	4855	2	0	0
T2	1794	1	0	0
T3	1783	9	0	0
T4	2302	6	0	0
T5	4480	6	0	0
T6	6985	10	0	0
T7	8871	1	0	0
T8	4638	2	0	0
T9	2052	6	0	0
T10	4364	6	0	0