Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_sys.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_usb.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_scanmode_sync	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_ctrl_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_io.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_sys.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_usb.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	16203	16203	0	0
OutputsKnown_A	408350755	238323188	0	0
gen_no_flops.OutputDelay_A	408350755	238323188	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16203	16203	0	0
T1	33	33	0	0
T2	33	33	0	0
T3	33	33	0	0
T4	33	33	0	0
T5	33	33	0	0
T6	33	33	0	0
T7	33	33	0	0
T8	33	33	0	0
T9	33	33	0	0
T10	33	33	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408350755	238323188	0	0
T1	160282	23349	0	0
T2	59243	38794	0	0
T3	59407	34122	0	0
T4	76209	44359	0	0
T5	148222	117017	0	0
T6	230705	19430	0	0
T7	292785	272104	0	0
T8	153120	22724	0	0
T9	68099	36764	0	0
T10	144252	112882	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408350755	238323188	0	0
T1	160282	23349	0	0
T2	59243	38794	0	0
T3	59407	34122	0	0
T4	76209	44359	0	0
T5	148222	117017	0	0
T6	230705	19430	0	0
T7	292785	272104	0	0
T8	153120	22724	0	0
T9	68099	36764	0	0
T10	144252	112882	0	0

Line Coverage for Instance : tb.dut.u_ctrl_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_ctrl_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	13873411	8352340	0	0
gen_no_flops.OutputDelay_A	13873411	8352340	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	8352340	0	0
T1	4922	821	0	0
T2	1835	1194	0	0
T3	2351	1706	0	0
T4	2545	1543	0	0
T5	4862	3833	0	0
T6	7185	774	0	0
T7	8913	8264	0	0
T8	4704	740	0	0
T9	2435	1404	0	0
T10	4604	3570	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	8352340	0	0
T1	4922	821	0	0
T2	1835	1194	0	0
T3	2351	1706	0	0
T4	2545	1543	0	0
T5	4862	3833	0	0
T6	7185	774	0	0
T7	8913	8264	0	0
T8	4704	740	0	0
T9	2435	1404	0	0
T10	4604	3570	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T9 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T9 

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	491	491	0	0
OutputsKnown_A	12327417	7186589	0	0
gen_no_flops.OutputDelay_A	12327417	7186589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491	491	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12327417	7186589	0	0
T1	4855	704	0	0
T2	1794	1175	0	0
T3	1783	1013	0	0
T4	2302	1338	0	0
T5	4480	3537	0	0
T6	6985	583	0	0
T7	8871	8245	0	0
T8	4638	687	0	0
T9	2052	1105	0	0
T10	4364	3416	0	0