Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T62
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T62,T13
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T62,T63
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T62
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T62,T63
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T62
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T62,T13
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13873411	14474	0	0
gen_assertions[0].RstEnOn_A	13873411	1124	0	0
gen_assertions[0].RstNOff_A	13873411	14474	0	0
gen_assertions[0].RstNOn_A	13873411	1124	0	0
gen_assertions[1].RstEnOff_A	55493001	13182	0	0
gen_assertions[1].RstEnOn_A	55493001	1066	0	0
gen_assertions[1].RstNOff_A	55493001	13182	0	0
gen_assertions[1].RstNOn_A	55493001	1066	0	0
gen_assertions[2].RstEnOff_A	27747553	13247	0	0
gen_assertions[2].RstEnOn_A	27747553	1071	0	0
gen_assertions[2].RstNOff_A	27747553	13247	0	0
gen_assertions[2].RstNOn_A	27747553	1071	0	0
gen_assertions[3].RstEnOff_A	27747404	13306	0	0
gen_assertions[3].RstEnOn_A	27747404	1125	0	0
gen_assertions[3].RstNOff_A	27747404	13306	0	0
gen_assertions[3].RstNOn_A	27747404	1125	0	0
gen_assertions[4].RstEnOff_A	1751434	22708	0	0
gen_assertions[4].RstEnOn_A	1751434	1170	0	0
gen_assertions[4].RstNOff_A	1751434	22708	0	0
gen_assertions[4].RstNOn_A	1751434	1170	0	0
gen_assertions[5].RstEnOff_A	13873411	14690	0	0
gen_assertions[5].RstEnOn_A	13873411	1197	0	0
gen_assertions[5].RstNOff_A	13873411	14690	0	0
gen_assertions[5].RstNOn_A	13873411	1197	0	0
gen_assertions[6].RstEnOff_A	13873411	14776	0	0
gen_assertions[6].RstEnOn_A	13873411	1285	0	0
gen_assertions[6].RstNOff_A	13873411	14776	0	0
gen_assertions[6].RstNOn_A	13873411	1285	0	0
gen_assertions[7].RstEnOff_A	13873411	14790	0	0
gen_assertions[7].RstEnOn_A	13873411	1297	0	0
gen_assertions[7].RstNOff_A	13873411	14790	0	0
gen_assertions[7].RstNOn_A	13873411	1297	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14474	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	4	0	0
T6	7185	0	0	0
T7	8913	1	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	5	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	4	0	0
T25	1682	0	0	0
T62	0	5	0	0
T63	0	3	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1124	0	0
T3	2351	3	0	0
T4	2545	0	0	0
T5	4862	0	0	0
T6	7185	0	0	0
T7	8913	1	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	1	0	0
T11	2028	0	0	0
T12	0	4	0	0
T25	1682	0	0	0
T36	0	3	0	0
T62	0	5	0	0
T63	0	3	0	0
T89	0	1	0	0
T91	0	6	0	0
T92	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14474	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	4	0	0
T6	7185	0	0	0
T7	8913	1	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	5	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	4	0	0
T25	1682	0	0	0
T62	0	5	0	0
T63	0	3	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1124	0	0
T3	2351	3	0	0
T4	2545	0	0	0
T5	4862	0	0	0
T6	7185	0	0	0
T7	8913	1	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	1	0	0
T11	2028	0	0	0
T12	0	4	0	0
T25	1682	0	0	0
T36	0	3	0	0
T62	0	5	0	0
T63	0	3	0	0
T89	0	1	0	0
T91	0	6	0	0
T92	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55493001	13182	0	0
T3	9408	8	0	0
T4	10185	4	0	0
T5	19455	4	0	0
T6	28744	0	0	0
T7	35657	2	0	0
T8	18820	0	0	0
T9	9743	4	0	0
T10	18424	3	0	0
T11	8117	0	0	0
T12	0	12	0	0
T13	0	4	0	0
T25	6735	0	0	0
T62	0	6	0	0
T63	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55493001	1066	0	0
T3	9408	3	0	0
T4	10185	0	0	0
T5	19455	0	0	0
T6	28744	0	0	0
T7	35657	2	0	0
T8	18820	0	0	0
T9	9743	0	0	0
T10	18424	0	0	0
T11	8117	0	0	0
T25	6735	0	0	0
T36	0	2	0	0
T57	0	1	0	0
T62	0	6	0	0
T63	0	2	0	0
T91	0	7	0	0
T92	0	2	0	0
T93	0	5	0	0
T94	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55493001	13182	0	0
T3	9408	8	0	0
T4	10185	4	0	0
T5	19455	4	0	0
T6	28744	0	0	0
T7	35657	2	0	0
T8	18820	0	0	0
T9	9743	4	0	0
T10	18424	3	0	0
T11	8117	0	0	0
T12	0	12	0	0
T13	0	4	0	0
T25	6735	0	0	0
T62	0	6	0	0
T63	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55493001	1066	0	0
T3	9408	3	0	0
T4	10185	0	0	0
T5	19455	0	0	0
T6	28744	0	0	0
T7	35657	2	0	0
T8	18820	0	0	0
T9	9743	0	0	0
T10	18424	0	0	0
T11	8117	0	0	0
T25	6735	0	0	0
T36	0	2	0	0
T57	0	1	0	0
T62	0	6	0	0
T63	0	2	0	0
T91	0	7	0	0
T92	0	2	0	0
T93	0	5	0	0
T94	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747553	13247	0	0
T3	4704	8	0	0
T4	5089	4	0	0
T5	9728	4	0	0
T6	14380	0	0	0
T7	17829	4	0	0
T8	9409	0	0	0
T9	4872	4	0	0
T10	9210	3	0	0
T11	4058	0	0	0
T12	0	12	0	0
T13	0	5	0	0
T25	3367	0	0	0
T62	0	9	0	0
T63	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747553	1071	0	0
T7	17829	4	0	0
T8	9409	0	0	0
T9	4872	0	0	0
T10	9210	0	0	0
T11	4058	0	0	0
T12	8687	0	0	0
T13	8729	1	0	0
T14	14688	0	0	0
T25	3367	0	0	0
T36	0	3	0	0
T53	0	1	0	0
T62	24222	9	0	0
T63	0	4	0	0
T91	0	9	0	0
T93	0	7	0	0
T94	0	5	0	0
T95	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747553	13247	0	0
T3	4704	8	0	0
T4	5089	4	0	0
T5	9728	4	0	0
T6	14380	0	0	0
T7	17829	4	0	0
T8	9409	0	0	0
T9	4872	4	0	0
T10	9210	3	0	0
T11	4058	0	0	0
T12	0	12	0	0
T13	0	5	0	0
T25	3367	0	0	0
T62	0	9	0	0
T63	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747553	1071	0	0
T7	17829	4	0	0
T8	9409	0	0	0
T9	4872	0	0	0
T10	9210	0	0	0
T11	4058	0	0	0
T12	8687	0	0	0
T13	8729	1	0	0
T14	14688	0	0	0
T25	3367	0	0	0
T36	0	3	0	0
T53	0	1	0	0
T62	24222	9	0	0
T63	0	4	0	0
T91	0	9	0	0
T93	0	7	0	0
T94	0	5	0	0
T95	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747404	13306	0	0
T3	4704	8	0	0
T4	5091	4	0	0
T5	9728	4	0	0
T6	14370	0	0	0
T7	17828	4	0	0
T8	9409	0	0	0
T9	4873	4	0	0
T10	9212	3	0	0
T11	4058	0	0	0
T12	0	12	0	0
T13	0	4	0	0
T25	3367	0	0	0
T62	0	9	0	0
T63	0	6	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747404	1125	0	0
T7	17828	4	0	0
T8	9409	0	0	0
T9	4873	0	0	0
T10	9212	0	0	0
T11	4058	0	0	0
T12	8687	0	0	0
T13	8728	0	0	0
T14	14681	0	0	0
T25	3367	0	0	0
T36	0	6	0	0
T53	0	1	0	0
T57	0	4	0	0
T62	24222	9	0	0
T63	0	6	0	0
T91	0	7	0	0
T93	0	8	0	0
T94	0	6	0	0
T96	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747404	13306	0	0
T3	4704	8	0	0
T4	5091	4	0	0
T5	9728	4	0	0
T6	14370	0	0	0
T7	17828	4	0	0
T8	9409	0	0	0
T9	4873	4	0	0
T10	9212	3	0	0
T11	4058	0	0	0
T12	0	12	0	0
T13	0	4	0	0
T25	3367	0	0	0
T62	0	9	0	0
T63	0	6	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27747404	1125	0	0
T7	17828	4	0	0
T8	9409	0	0	0
T9	4873	0	0	0
T10	9212	0	0	0
T11	4058	0	0	0
T12	8687	0	0	0
T13	8728	0	0	0
T14	14681	0	0	0
T25	3367	0	0	0
T36	0	6	0	0
T53	0	1	0	0
T57	0	4	0	0
T62	24222	9	0	0
T63	0	6	0	0
T91	0	7	0	0
T93	0	8	0	0
T94	0	6	0	0
T96	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	22708	0	0
T1	614	2	0	0
T2	229	1	0	0
T3	293	8	0	0
T4	318	5	0	0
T5	607	6	0	0
T6	901	3	0	0
T7	1113	6	0	0
T8	587	2	0	0
T9	303	5	0	0
T10	574	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	1170	0	0
T7	1113	5	0	0
T8	587	0	0	0
T9	303	0	0	0
T10	574	1	0	0
T11	252	0	0	0
T12	541	0	0	0
T13	545	0	0	0
T14	921	0	0	0
T25	210	0	0	0
T36	0	4	0	0
T57	0	4	0	0
T62	1512	11	0	0
T63	0	5	0	0
T91	0	10	0	0
T93	0	10	0	0
T94	0	8	0	0
T96	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	22708	0	0
T1	614	2	0	0
T2	229	1	0	0
T3	293	8	0	0
T4	318	5	0	0
T5	607	6	0	0
T6	901	3	0	0
T7	1113	6	0	0
T8	587	2	0	0
T9	303	5	0	0
T10	574	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1751434	1170	0	0
T7	1113	5	0	0
T8	587	0	0	0
T9	303	0	0	0
T10	574	1	0	0
T11	252	0	0	0
T12	541	0	0	0
T13	545	0	0	0
T14	921	0	0	0
T25	210	0	0	0
T36	0	4	0	0
T57	0	4	0	0
T62	1512	11	0	0
T63	0	5	0	0
T91	0	10	0	0
T93	0	10	0	0
T94	0	8	0	0
T96	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14690	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	4	0	0
T6	7185	0	0	0
T7	8913	6	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	4	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	4	0	0
T25	1682	0	0	0
T62	0	12	0	0
T63	0	8	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1197	0	0
T7	8913	6	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	0	0	0
T11	2028	0	0	0
T12	4342	0	0	0
T13	4364	0	0	0
T14	7341	0	0	0
T25	1682	0	0	0
T36	0	8	0	0
T53	0	1	0	0
T57	0	5	0	0
T62	12110	12	0	0
T63	0	8	0	0
T91	0	12	0	0
T93	0	10	0	0
T94	0	9	0	0
T97	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14690	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	4	0	0
T6	7185	0	0	0
T7	8913	6	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	4	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	4	0	0
T25	1682	0	0	0
T62	0	12	0	0
T63	0	8	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1197	0	0
T7	8913	6	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	0	0	0
T11	2028	0	0	0
T12	4342	0	0	0
T13	4364	0	0	0
T14	7341	0	0	0
T25	1682	0	0	0
T36	0	8	0	0
T53	0	1	0	0
T57	0	5	0	0
T62	12110	12	0	0
T63	0	8	0	0
T91	0	12	0	0
T93	0	10	0	0
T94	0	9	0	0
T97	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14776	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	5	0	0
T6	7185	0	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	4	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	5	0	0
T25	1682	0	0	0
T62	0	12	0	0
T63	0	8	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1285	0	0
T5	4862	1	0	0
T6	7185	0	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	0	0	0
T11	2028	0	0	0
T12	4342	0	0	0
T13	0	1	0	0
T14	7341	0	0	0
T25	1682	0	0	0
T36	0	9	0	0
T62	0	12	0	0
T63	0	8	0	0
T91	0	11	0	0
T93	0	12	0	0
T94	0	9	0	0
T95	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14776	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	5	0	0
T6	7185	0	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	4	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	5	0	0
T25	1682	0	0	0
T62	0	12	0	0
T63	0	8	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1285	0	0
T5	4862	1	0	0
T6	7185	0	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	0	0	0
T11	2028	0	0	0
T12	4342	0	0	0
T13	0	1	0	0
T14	7341	0	0	0
T25	1682	0	0	0
T36	0	9	0	0
T62	0	12	0	0
T63	0	8	0	0
T91	0	11	0	0
T93	0	12	0	0
T94	0	9	0	0
T95	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14790	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	4	0	0
T6	7185	0	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	4	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	5	0	0
T25	1682	0	0	0
T62	0	13	0	0
T63	0	9	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1297	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	0	0	0
T11	2028	0	0	0
T12	4342	0	0	0
T13	4364	1	0	0
T14	7341	0	0	0
T25	1682	0	0	0
T36	0	9	0	0
T53	0	1	0	0
T57	0	8	0	0
T62	12110	13	0	0
T63	0	9	0	0
T91	0	12	0	0
T93	0	11	0	0
T94	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	14790	0	0
T3	2351	8	0	0
T4	2545	4	0	0
T5	4862	4	0	0
T6	7185	0	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	4	0	0
T10	4604	4	0	0
T11	2028	0	0	0
T12	0	13	0	0
T13	0	5	0	0
T25	1682	0	0	0
T62	0	13	0	0
T63	0	9	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13873411	1297	0	0
T7	8913	8	0	0
T8	4704	0	0	0
T9	2435	0	0	0
T10	4604	0	0	0
T11	2028	0	0	0
T12	4342	0	0	0
T13	4364	1	0	0
T14	7341	0	0	0
T25	1682	0	0	0
T36	0	9	0	0
T53	0	1	0	0
T57	0	8	0	0
T62	12110	13	0	0
T63	0	9	0	0
T91	0	12	0	0
T93	0	11	0	0
T94	0	9	0	0